AD9546SLASHPCBZ datasheet(94/205 Pages) AD

94 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 94 of 205

DISTRIBUTION DIVIDERS (Q DIVIDERS)

DISTRIBUTION DIVIDERS OVERVIEW

Five pairs of Q dividers correspond to the five pairs of clock

output drivers (see the Distribution Clock Output Drivers

section). Unlike typical clock dividers, which count the rising

edge (or falling edge) of its input clock, the Q dividers count

both the rising and falling edges of its input clock. Dual-edge

counting enables features not possible with a typical counter.

The Q dividers respond to several controllers that implement

the various features of the Q dividers. Figure 67 shows a

diagram of the Q dividers and associated controllers. Although

not explicitly shown, the output of each Q divider routes to its

corresponding output driver.

Each Q divider has independent phase offset (delay) capability

as governed by a phase offset controller (see the Distribution

Phase Offset Control section). In addition, a sophisticated and

flexible synchronization mechanism provides synchronized

output clock timing for any or all Q divider output signals (see

the Distribution Output Clock Synchronization section).

A JESD204B and burst controller enables each Q divider to

generate a clock signal supporting JESD204B or to generate

flexible burst patterns supporting gapped clock and similar

applications (see the Distribution N Shot/PRBS Output

Clocking section).

Furthermore, the Qxy divider of each Q divider pair is capable

of modulating (that is, time shifting) falling edges of the output

clock signal. The modulation of the clock edge location

supports embedded clock applications such as transporting a

lower frequency clock signal over a higher frequency carrier

clock (see the Distribution Embedded Output Clock

Modulation section).

At power-up, the synchronization controller holds the disabled

Q dividers (that is, there are no output clocks). Consequently,

the user must issue a synchronization request (see the

Distribution Output Clock Synchronization section) following

a power-up or reset to initialize the Q dividers.

MODULATION

Qxy

SYNC

Qxy

SYSTEM

CLOCK

PLL0/PLL1

P DIVIDER

Q DIVIDER PAIR 1

Q DIVIDER PAIR 5

OUTPUT

DRIVERS

N SHOT/PRBS

CONTROLLER

PHASE OFFSET

CONTROLLER

SYNCHRONIZATION

CONTROLLER

TO Q DIVIDER PAIR 2 TO PAIR 5

MODULATION

CONTROLLER

N SHOT/PRBS

PHASE OFFSET

SYNC

Figure 67. Functional Block Diagram of Q Dividers and Controllers

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