AD9546SLASHPCBZ datasheet(87/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 87 of 205

REFERENCE DEMODULATOR

REFERENCE DEMODULATOR OVERVIEW

The AD9546 has eight reference demodulators: one for each

REFx input and one for each auxiliary REFx input (see the

Reference Clock Input Resources section). The REFx receivers

are configurable as single-ended or differential. The auxiliary

REFx receivers are single-ended only (nonconfigurable).

When REFA is configured for differential operation, only the

demodulator associated with REFA is available (the

demodulator associated with REFAA is unused). The same

applies for REFB.

When enabled, a demodulator recognizes modulated carrier

cycles on its associated reference input clock (a modulated cycle

is a phase deviation imposed on the falling edge of an input

clock cycle). The demodulator is compatible with embedded

clock signals generated by Analog Devices clock chips that

support embedded output clock modulation (the AD9545, for

example). For details on embedded clock modulation, see the

Distribution Embedded Output Clock Modulation section.

Figure 62 shows a basic block diagram of the reference

demodulator (legacy mode). The Letter X denotes a reference

demodulator associated with a specific reference input, and M

and N associate a specific register address with Demodulator X

per the register legend in Figure 62.

Referring to Figure 62, the reference input clock signal passes

through the reference receiver and drives the clock input of the

reference divider as well as the demodulator input. When the

input reference signal carries embedded clock modulation

events, the demodulator provides a means of detecting them.

On detection of a modulation event on its input clock, the

demodulator synchronizes the associated reference divider and

causes the associated reference TDC to tag the time stamp

generated by the modulation event.

INTERACTION BETWEEN DEMODULATOR AND

REFERENCE MONITOR

The reference monitor validates based on the input carrier

signal. However, the first modulation event after enabling the

reference demodulator causes a resynchronization of the

R divider. The resynchronization of the R divider starts a new

reference monitor validation sequence, which means the

reference invalidates. The user has access to the resynchronization

strobe via an appropriately configured Mx pin.

The resynchronization of the R divider is a singular event that

happens when the demodulator must force the R divider to

reset on grid (see the Demodulator Synchronization section

regarding the modulation grid). Thus, after enabling the

reference demodulator, to avoid the disruption of reference

validation due to the resynchronization of the R divider, use a

reference validation timer value greater than the period

between modulation events (see the Validation Time (tVALID)

section).

EXPECTED POLARITY

REFERENCE

RECEIVER

SENSITIVITY

Mx PIN

FUNCTION

LOGIC

PINS

BANDWIDTH

TO THREE OTHER

DEMODULATORS

DEMOD CLK

DEMOD IN

SYNC EDGE

AUTOMATIC POLARITY DETECT

DEMODULATOR X

PERSISTENCE

REFERENCE

INPUT

ENABLE

SYNC

TEXT

= BIT(S) IN THE REGISTER MAP

TIME

STAMPS

REFA

REFAA

REFB

REFBB

AUX REF0

AUX REF2

AUX REF3

0x0302

0x0303

0x0306

0x0307

0x030 A

0x030 B

0x030 E

0x030F

0x0301

0x0305

TDC

TAG

REF INPUT

REFERENCE

DIVIDER

AUX REF1

Figure 62. Reference Demodulator: Legacy Mode

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