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AD9546/PCBZ 数据表(PDF) 67 Page - Analog Devices |
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AD9546/PCBZ 数据表(HTML) 67 Page - Analog Devices |
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67 / 205 page  Data Sheet AD9546 Rev. 0 | Page 67 of 205 Table 43. UTS Channel Flag Assignments Flags Bit Field, Bits[4:2] Bit 4 Status Encode Bit 3 Status Encode Bit 2 Status Encode 000 (Default) Tag Invalid Unlocked 001 Tag Fault Unlocked 010 Format Invalid Unlocked 011 Format Fault Unlocked 100 Fault Invalid Unlocked 101 Format Tag Unlocked or invalid 110 Format Tag Unlocked or fault 111 Unused Unused Unused UTS READBACK FIFO The UTS system uses a FIFO to collect time code samples (up to 18) from all enabled UTS channels. The FIFO allows queuing of time codes arriving from the various UTS channels for readback by the user via the register map. Each FIFO sample consists of the following: • 96-bit time code • 3-bit encoded status code • 5-bit source code Time Code The 96-bit time code appears in Register 0x0E2F to Register 0x0E3A, which adheres to the same functionality as Register 0x0F0A to Register 0x0F15 described in the Synchronization Time subsection of the Common Clock Synchronizer (CCS) section. Note that interpretation of the time code requires knowledge of the underlying format (fractional seconds or PTP). There are two ways to discern the format of a time code sample. One way is to use the source code information (see the Source Code section) to determine which UTS is the source of the time code sample and then read the state of the format bit in the appropriate UTS Channel x control register (where x is 0 to 8, integer). Another way is to use one of the seven predefined encoded status patterns that includes the format status in Table 43. In this method, the encoded status code (see the Encoded Status section) contains the format information for the time code sample. Source Code A 5-bit source code bit field accompanies each time code. The source code appears in Bits[4:0] of Register 0x0E2E. The source code value for a given time code sample indicates the time stamp source shown in Table 42. The source code that accompanies a time code is identical to the source code assignment of the UTS channel associated with the time code (see the UTS Channel Time Stamp Source section). The source code does not indicate the UTS channel associated with the time code, but the original source of the time stamp. Encoded Status A 3-bit encoded status flags bit field (Bits[7:5] of Register 0x0E2E) accompanies each time code. The meaning of each bit depends on the flags bit field of the UTS channel associated with the time code sample in accordance with Table 44. To determine the meaning of each of the three bits, the user must be aware of which UTS channel provided the time code (see the Source Code section) and the state of the 3-bit flags bit field associated with that UTS channel (see the UTS Channel Status Flag Assignment section). Table 44. UTS FIFO Readback Encoded Status Bits Bits[4:2]1 Bit 7 Encoded Status Bit 6 Encoded Status Bit 5 Encoded Status 000 Tag Invalid Unlocked 001 Tag Fault Unlocked 010 Format Invalid Unlocked 011 Format Fault Unlocked 100 Fault Invalid Unlocked 101 Format Tag Unlocked or invalid 110 Format Tag Unlocked or fault 111 Unused Unused Unused 1 Bits[4:2] in the UTS Channel x control register associated with the time code. UTS FIFO Status Because the FIFO effectively works in the background collecting UTS time codes, the FIFO provides the user with a continuous status of the current state. The status information is essential to keep the user aware of how frequently to read FIFO samples or if sample data is lost due to an overflow condition. There are two categories of status information: FIFO overfill (a single status bit) and FIFO count (7-bit field). FIFO Overfill The FIFO overfill bit in Bit 7 of Register 0x0E2D indicates that the FIFO has exceeded the capacity, where Logic 1 indicates overfill. When the FIFO asserts the overfill bit, any time codes arriving at the FIFO input are lost. The state of the FIFO overfill bit appears as part of the IRQ mechanism (see the Interrupt Request (IRQ) section) via Bit 7 of Register 0x301C. The overfill status of the FIFO is also available via an appropriately configured Mx status pin (see the Status and Control Pins section). The FIFO overfill bit and Mx pin status (if configured) clear when the user reads a sample from the FIFO. |
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