AD9546SLASHPCBZ datasheet(8/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 8 of 205

POWER DISSIPATION

The typical values apply for VDD = 1.8 V, and the maximum values apply for VDD = 1.89 V.

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER DISSIPATION

fOSC is the frequency at the XOA/XOB pins

Typical Configuration

585

760

fOSC = 49.152 MHz crystal; two active DPLLs;

two 19.44 MHz input references in differential mode;

two ac-coupled PLL Channel 0 (PLL0) current mode logic

(CML) output drivers at 245.76 MHz; and two PLL Channel 1

(PLL1) CML output drivers at 156.25 MHz

Line Card Configuration

585

760

fOSC = 52 MHz crystal; two active DPLLs (hitless mode); five

single-ended input references with two operating at 10 MHz

and three with active 1 Hz reference demodulation operating

at 50 MHz; five HCSL (15 mA) output drivers operating at

10 MHz; one auxiliary NCO operating at 500 Hz; two inverse

user timer stampers (IUTSs) operating at 500 Hz; auxiliary

DPLL enabled; see the Digitized Clocking Application section

for line card information

Timing Card Configuration

585

760

fOSC = 52 MHz crystal; two active DPLLs (one hitless mode, one

phase build-out mode); eight single-ended input references

with four operating at 10 MHz and four with active 1 Hz

reference demodulation operating at 50 MHz; five HCSL

(15 mA) output drivers with two operating at 10 MHz and

three with active 1 Hz embedded clock modulation operating

at 50 MHz; two auxiliary NCOs with one operating at 500 Hz

and one operating at 1 Hz; one IUTS operating at 500 Hz;

auxiliary DPLL enabled; see the Digitized Clocking Application

section for timing card information

All Blocks Running Configuration

745

795

fOSC = 49.152 MHz crystal; two active DPLLs;

two 19.44 MHz input references in differential mode;

three ac-coupled PLL0 HCSL output drivers at 400 MHz; and

two PLL1 HCSL output drivers at 400 MHz

Full Power-Down

125

Based on the Typical Configuration specification, but with

Incremental Power Dissipation

Based on the Typical Configuration specification; the values in

this section indicate the change in power due to the indicated

operation relative to the Typical Configuration specification

Complete DPLL/APLL On vs. Off

160

Change in dissipated power relative to the Typical Configuration

specification; the powered down blocks consist of one reference

input, one DPLL, one APLL, two channel dividers, and two

output drivers

Input Reference On vs. Off

Differential (AC-Coupled Mode)

Reference frequency (fREF) = 19.44 MHz (see Figure 36)

Differential (DC-Coupled Mode)

fREF = 19.44 MHz (see Figure 37)

Single-Ended

fREF = 19.44 MHz

Output Distribution Driver On vs. Off

At 156.25 MHz

15 mA Mode

12.5 mA Mode

7.5 mA Mode

Auxiliary DPLL On vs. Off

Auxiliary Numerically Controlled

Oscillator (NCO) to Mx Pin On vs. Off

Fundamental set to 50 kHz

Auxiliary Time to Digital Converter

(TDC) Input from Mx Pin On vs. Off

Input frequency (fIN) = 10 MHz, auxiliary TDC rate = 200 kHz

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