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AD9546/PCBZ 数据表(PDF) 19 Page - Analog Devices |
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AD9546/PCBZ 数据表(HTML) 19 Page - Analog Devices |
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19 / 205 page  Data Sheet AD9546 Rev. 0 | Page 19 of 205 OUTPUT TO OUTPUT TIMING SKEW The values in Table 12 indicate the time offset of the target output clock edge relative to the base output clock edge. fREF = 25 MHz; fREF applied to a single reference input with that reference assigned to Digital Phase-Locked Loop 0 (DPLL0) and Digital Phase-Locked Loop 1 (DPLL1); DPLL0 and DPLL1 operate in zero delay (hitless mode); PLL0 and PLL1 frequency translation is such that the frequency of the OUTxyP and OUTxyN pins (fOUTxy) = fREF for all outputs. Table 12. Parameter Min Typ Max Unit TARGET OUTPUT1 OUT1A Differential CML Base Output OUT0A Differential CML −21 +53 +123 ps Differential HCSL −89 −36 +14 ps OUT1A Differential HCSL Base Output OUT0A Differential CML 3 83 174 ps Differential HCSL −61 −5 +50 ps OUT1A Single-Ended CML Base Output OUT0A Differential CML −24 +48 +109 ps Differential HCSL −120 −43 +25 ps Single-Ended CML −18 +63 +123 ps Single-Ended HCSL −132 −56 +8 ps OUT1A Single-Ended HCSL Base Output OUT0A Differential CML 93 175 254 ps Differential HCSL 16 84 190 ps Single-Ended CML 92 191 282 ps Single-Ended HCSL 0 77 134 ps OUT0B or OUT0C Differential CML Base Output OUT0A Differential CML 37 60 97 ps Differential HCSL −67 −30 +2 ps OUT0B or OUT0C Differential HCSL Base Output OUT0A Differential CML 53 87 118 ps Differential HCSL −25 −3 +22 ps OUT0B or OUT0C Single-Ended CML Base Output OUT0A Differential CML 15 44 66 ps Differential HCSL −84 −48 −21 ps Single-Ended CML 37 67 98 ps Single-Ended HCSL −100 −53 −24 ps OUT0B or OUT0C Single-Ended HCSL Base Output OUT0A Differential CML 135 175 212 ps Differential HCSL 53 80 112 ps Single-Ended CML 162 198 273 ps Single-Ended HCSL 46 79 104 ps 1 OUTxy refers to Output xy where x is 0 or 1, and y is A, B, or C. See the Distribution Clock Output Drivers Overview section for more information about the output drivers. |
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