AD9546SLASHPCBZ datasheet(74/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 74 of 205

SYSTEM CLOCK PLL

SYSTEM CLOCK PLL OVERVIEW

The system clock PLL (see Figure 57) comprises an Integer N

frequency synthesizer with a fully integrated loop filter and

VCO. The VCO output is the AD9546 system clock with a

frequency range of 2250 MHz to 2415 MHz. The XOA and

XOB pins constitute the input to the system clock PLL to which

a user connects a clock source or crystal resonator.

VCO

CALIBRATION

LOCK

DETECTOR

SYSTEM

CLOCK

XOA

XTAL

DIRECT

2250MHz TO

2415MHz

XOB

2×

÷J

÷K

1, 2, 4, 8

4 TO 255

PFD,

CHARGE PUMP,

LOOP FILTER

AD9546

Figure 57. System Clock PLL Block Diagram

SYSTEM CLOCK INPUT FREQUENCY

DECLARATION

Proper operation of the AD9546 requires the user to declare the

input reference frequency to the system clock PLL by

programming the 40-bit unsigned integer in Bits[39:0] of Register

0x0206 to Register 0x0202. The programmed value constitutes the

nominal frequency, in units of mHz, applied to the XOA and

XOB pins. The AD9546 evaluation software frequency

planning wizard calculates this value for the user.

SYSTEM CLOCK SOURCE

The XOA and XOB pins serve as the input connection to the

system clock PLL, giving the user access to a crystal path (see

Figure 30) or a direct path (see Figure 31). Path selection is via

direct path and Logic 1 selects the crystal path. The optimal

reference source for the system clock input is a crystal

resonator in the 50 MHz range or an ac-coupled square wave

source (single-ended or differential) with an 800 mV p-p

amplitude.

Crystal Path

Select the crystal path by programming Register 0x0201, Bit 3, to

Logic 1. Refer to Figure 30 for connecting a crystal resonator to

the XOA and XOB pins. The CTUNE capacitors shown in Figure 30

relate to CLOAD and CSTRAY as follows:

CTUNE = 2 × (CLOAD – CSTRAY)

where:

CTUNE is a tuning capacitor.

CLOAD is the load capacitance, per the specification of the crystal

manufacturer.

CSTRAY is any additional parasitic capacitance.

As an example, when CLOAD = 10 pF and CSTRAY = 2 pF to 5 pF,

the value of CTUNE is approximately 15 pF.

The crystal path supports crystal resonators in the 25 MHz to

80 MHz frequency range. An internal maintaining amplifier

provides the negative resistance required to induce oscillation.

The internal amplifier expects an AT cut, fundamental mode

crystal with a maximum motional resistance of 100 Ω for

crystals up to 52 MHz, and 50 Ω for crystals up to 80 MHz. The

following crystals, listed in alphabetical order, may meet these

criteria:

•

AVX/Kyocera CX3225SB

•

ECS, Inc. ECX-32

•

Epson/Toyocom TSX-3225

•

Fox FX3225BS

•

NDK NX3225SA

•

Siward SX-3225

•

Suntsu SCM10B48-49.152 MHz

Analog Devices, Inc., does not guarantee the operation of the

AD9546 with these crystals, nor does Analog Devices endorse

one crystal supplier over another. The AD9546 reference design

uses a readily available high performance 49.152 MHz crystal

with low spurious content.

Crystal resonators are subject to the specified maximum power

dissipation requirement of the manufacturer. As such, some

crystal resonators may require the use of a resistor to absorb

some of the power delivered by the maintaining amplifier to

satisfy the maximum power dissipation requirement of the

crystal resonator. Figure 58 shows the proper way to connect

the power limiting resistor, RLIMIT, to achieve optimal performance.

XOA

XOB

AD9546

CTUNE

RLIMIT

Figure 58. Power Limiting Resistor Connection

Frequency Doubler (2× Multiplier)

When a crystal resonator is the frequency source to the system

clock, the user has the option of doubling the reference

frequency via Bit 0 of Register 0x0201. Programming a Logic 1

doubles the input reference frequency to the system clock PLL,

which improves the in-band noise of the PLL by 2 dB to 3 dB.

The frequency doubler cannot be used with the direct path

input of the system clock PLL.

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