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AD9546/PCBZ 数据表(PDF) 59 Page - Analog Devices |
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AD9546/PCBZ 数据表(HTML) 59 Page - Analog Devices |
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59 / 205 page  Data Sheet AD9546 Rev. 0 | Page 59 of 205 COMMON CLOCK SYNCHRONIZER (CCS) OVERVIEW COMMON TIME SCALE LOCAL TIME SCALE SKEW SYNC TIME SYNC OFFSET REFINEMENT SLEW LIMITER RESTART SLEW LIMIT GUARD GUARD BYPASS LOCK STATUS INITIAL SYNC DETECT MAXIMUM MAGNITUDE DETECT GUARD ADJUSTMENT OFFSET STATUS EVENT DETECT COMMON CLOCK DPLL LOCK STATUS LATENCY DETECT SYSTEM CLOCK STABILITY STATUS SYNC TIME ACTIVE SOURCE INDEX (0,1) FROM THE COMMON CLOCK DPLL INITIAL SYNC TIME OF DAY SOURCE GUARD LATENCY NORMALLY CLOSED SYNC OFFSET VALUES UPDATE ON EACH VALID SYNC EVENT VALID SYNC TIME STAMP SYNC OFFSET REFINEMENT SLEW LIMITER SUMMING NODE REG 0x0D11, BITS[4:0] REG 0x0D21, BITS[4:0] 0 1 REG 0x0D1D TO 0x0D1B, BITS[23:0] REG 0x0D2D TO 0x0D2B, BITS[23:0] 0 1 REG 0x0D33 TO 0x0D30, BITS[31:0] REG 0x0D36 TO 0D34, BITS[23:0] REG 0x0D38 TO 0x0D37, BITS[15:0] REG 0x0D3C, BIT 0 REG 0x0D3B TO 0x0D39, BITS[19:0] TIME OF DAY SOURCE TAG REG 0x0D11, BIT 7 REG 0x0D21, BIT 7 0 1 CSS SYNC 0 TIME CODE CSS SYNC 1 TIME CODE 0 1 FROM IUTS 96 96 0 1 CSS SYNC 1 RESTART CSS SYNC 0 RESTART RESTART TAG DETECT SYNC EVENT TIME STAMPS NOTES 1. A RANGE OF BITS USES A COLON SEPARATOR Figure 51. Common Clock Synchronizer The CCDPLL phase locks to a physical common clock source (the common clock reference) and generates an internal local time scale. The local time scale constitutes time as the accumulation of the period of the system clock as defined by the system clock input frequency programmed by the user. The CCDPLL relies on a crystal resonator (via the XOA and XOB pins) for internal timing, which is a relatively unstable frequency source. However, the architecture of the CCDPLL allows it to phase lock to the common clock reference even with the relative instability of the crystal resonator. Thus, the local time scale is immune to instability associated with the frequency source of the system clock. Because the CCDPLL derives its timing from the system clock but the phase locks to the common clock reference, instabilities associated with either source contribute to the loop stability of the CCDPLL. Thus, the user must tailor the loop bandwidth of the CCDPLL in accordance with the combined stability of the system clock and common clock reference frequencies. The frequency stability of the sources puts a limit on the minimum allowable loop bandwidth that yields a stable loop and minimizes the phase offset associated with the ability of the PLL to track frequency variations. |
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