AD9546SLASHPCBZ datasheet(63/205 Pages) AD

63 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 63 of 205

For example, to set latency detection value to 1 ms (10−3 sec),

first convert to the appropriate units and round the result to the

nearest integer as follows:

10−3 × 216 = 66

This value in 16-bit hexadecimal format is: 0x 0042.

SYNCHRONIZATION SLEW LIMITER

A typical digitized clocking system sometimes experiences the

injection of a relatively large phase adjustment as part of the

common clock synchronization process. An example is the

injection of a phase jump due to switching between two CCRs

having a static phase offset (see the Common Clock Reference

Switchover section). Another example is a phase jump due to

the injection of a phase adjustment to compensate for round

trip delay in a clock signal path (see the Analog Clock

Loopback section). Phase adjustments constitute instantaneous

phase jumps, which equate to frequency impulses. The

frequency impulses transfer to the common time scale via the

action of the CCS.

To mitigate the frequency impulses resulting from phase

adjustments, the CCS provides a slew limiter following the

synchronization offset refinement block (see Figure 51). The

slew limiter converts large phase jumps (frequency impulses) to

a constant phase slope (which equates to a constant frequency

offset). Thus, the action of the slew limiter puts a user defined

upper bound on the frequency deviation associated with a

phase adjustment. Because the slew limiter is physically situated

at the output of the CCS (see Figure 51), it effectively limits the

magnitude of the frequency offset injected on the common time

scale as the result of a phase adjustment.

The user activates the slew limiter by writing a nonzero value to

the 24-bit unsigned slew limit value in Register 0x0D34 to

constrain the frequency deviation on the common time scale to

a maximum of 0.15 ppm (1.5 × 10−7), first convert to the

appropriate units and round the result to the nearest integer as

follows:

1.5 × 10−7 × 236 = 10,308

This value in 24-bit hexadecimal format is: 0x 00 2844.

When the user programs a new slew limit value, the slew

limiter stalls briefly while implementing the slew limit value

change. From an application perspective, the stalling behavior

is inconsequential.

The user can bypass the slew limiter at any time by

programming a slew limit value of zero. The slew limiter

automatically bypasses for the initial application of a

synchronization offset value. However, subsequent

synchronization offset values are subject to slew limiting

(assuming the user programs a nonzero slew limit value).

The status of the slew limiter is available via several mechanisms.

Bit 6 of Register 0x0D40 is Logic 1 when the slew limiter is

actively slewing and Logic 0 when it is not slewing. The status

of the slew limiter is also available via an appropriately

configured Mx status pin (see the Status and Control Pins

section). In addition, slew limiter status is available as part of

the IRQ mechanism (see the Interrupt Request (IRQ) section)

via Bit 2 and Bit 3 of Register 0x301D, which indicate when the

slew limiter starts and stops slewing, respectively.

RESTART

When a synchronization restart occurs, the next generated

synchronization offset value propagates through the refinement

block unaltered, with subsequent synchronization offset values

receiving progressively more filtering over time. The user can

manually restart the synchronization offset refinement process

from the beginning at any time by programming Bit 0 of Register

0x0F08 to Logic 1.

The synchronization event that follows a synchronization

restart is not the same as an initial synchronization event (a

synchronization event following a device power-up, for example).

Thus, a synchronization restart does not cause the slew limiter

to bypass automatically on the first synchronization event

following a synchronization restart.

SYNCHRONIZATION GUARD

Because common clock synchronization has a direct impact on

the common time scale, safeguards are in place to mitigate

corruption of the common time scale with invalid synchroniza-

tion events. Such is the function of the guard element shown in

Figure 51. Conceptually, the guard controls a normally closed

switch that opens when the guard detects a guard event, thereby

preventing the most recent synchronization offset value from

propagating into the synchronization offset refinement process.

Assuming the initial synchronization has occurred (see the

Initial Synchronization section), the following three conditions

can trigger the synchronization guard to open the guard switch:

•

The common clock DPLL unlocks (assuming the guard

bypass lock bit is not set)

•

A maximum magnitude detection event

•

A latency detection event

Any one of these conditions trips the synchronization guard,

which causes a synchronization error. To check the

synchronization error status, use Bit 7 of Register 0x0D40,

where Logic 1 indicates a synchronization error. Synchronization

error status is also available via an appropriately configured Mx

status pin (see the Status and Control Pins section) and via Bit 1

of Register 0x301D as part of the IRQ mechanism (see the

Interrupt Request (IRQ) section).

AD9546/PCBZ 数据表(PDF) 63 Page - Analog Devices

AD9546/PCBZ 数据表(HTML) 63 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载