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AD9546/PCBZ 数据表(PDF) 11 Page - Analog Devices |
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AD9546/PCBZ 数据表(HTML) 11 Page - Analog Devices |
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11 / 205 page  Data Sheet AD9546 Rev. 0 | Page 11 of 205 Parameter Min Typ Max Unit Test Conditions/Comments Input Voltage High, VIH 1.17 2.07 V Low, VIL 0.63 V Input Resistance 30 kΩ Slew Rate >8 V/µs Required for proper reference monitor operation; output jitter degradation can occur for slew rates <35 V/µs Input Pulse Width 900 ps AC-Coupled Frequency Range 1 500 × 106 Hz Applies to 1.2 V CMOS ac-coupled Input Amplitude 360 1200 mV Peak-to-peak single-ended voltage swing; instantaneous voltage must not exceed 1.3 V Input Impedance 15 kΩ Input Pulse Width 900 ps Slew Rate >8 V/µs Required for proper reference monitor operation; output jitter degradation can occur for slew rates < 35 V/µs Common-Mode Voltage 610 mV Internally generated self bias voltage; applies to 1.2 V CMOS ac-coupled AUXILIARY REFERENCES Applies to the auxiliary Reference 0 (REF0) to auxiliary Reference 3 (REF3) inputs via appropriately configured Mx control pins (see the Reference Clock Input Resources section) Frequency Range 225 MHz Input Voltage High, VIH VDDIOx − 0.4 V Low, VIL 0.4 V Slew rate >8 V/µs Required for proper reference monitor operation; output jitter degradation can occur for slew rates < 35 V/µs; applies for VDDIOB = 1.8 V, 2.5 V, or 3.3 V REFERENCE DEMODULATOR fOUT is the Q divider output frequency; fSYS is the system clock frequency and must be in the 2250 MHz to 2415 MHz range; fSYS = fOSC × K/J, where fOSC is the frequency of the system clock oscillator connected to the XOA/XOB pins, K is the feedback divider ratio, and J is the system clock (SYSCLK) input scale factor; when the SYSCLK doubler is disabled, J is the value of the J divider (1, 2, 4, or 8); when the SYSCLK doubler is enabled, J = ½ Carrier Frequency (Synchronization Edge = 1, 2, 3) Band 0 and Band 1 (see the Demodulator Bandwidth section) Band 0 DC Balanced Modulation 0.5 40 MHz Unbalanced Modulation 0.5 60 MHz Band 1 DC Balanced Modulation 1 120 MHz Unbalanced Modulation 1 180 MHz Embedded Clock Rate 1 fCAR/8 Hz fCAR is the unmodulated input frequency Duty Cycle Deviation S is the decimal value of Bits[1:0] in Register 0x0302, Register 0x0303, Register 0x0306, or Register 0x0307 (see the Demodulator Sensitivity section); B depends on the selected band, where B is fSYS/3 for Band 0 or fSYS for Band 1 (see the Demodulator Bandwidth section) DC Balanced Modulation (5 + S)/3B 1/(4fCAR) sec Unbalanced Modulation (5 + S)/2B 1/(4fCAR) sec Polarity Detection Enabled (5 + S)/B 1/(4fCAR) sec |
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