HC705JJ7GRSSLASHD datasheet(151/230 Pages) NXP

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Core Timer

Core Timer Counter Register (CTCR)

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Core Timer

10.4 Core Timer Counter Register (CTCR)

A 15-stage ripple counter driven by a divide-by-eight prescaler is the

basis of the core timer. The value of the first eight stages is readable at

any time from the read-only timer counter register as shown in

Figure 10-3.

Power-on clears the entire counter chain and begins clocking the

counter. After the startup delay (16 or 4064 internal bus cycles

depending on the DELAY bit in the mask option register (MOR)), the

power-on reset circuit is released, clearing the counter again and

allowing the MCU to come out of reset.

Table 10-1. Core Timer Interrupt Rates and COP Timeout Selection

Timer Overflow

Interrupt Period

TOF = 1/(fOSC ÷ 2

11)

(microseconds)

RT1 RT0

RTI

Rate

= fOSC

divided

by:

Real-Time

Interrupt Period

(RTI)

(milliseconds)

COP Timeout Period

COP = 7 to 8 RTI Periods

(milliseconds)

@ fOSC (MHz)

4.2

MHz

2.0

MHz

1.0

MHz

4.2

MHz

2.0

MHz

1.0

MHz

4.2 MHz

2.0 MHz

1.0 MHz

Min

Max

Min

Max

Min

Max

488

1024

2048

215

7.80

16.4

32.8

54.6

62.4

115

131

229

262

216

15.6

32.8

65.5

109

125

229

262

459

524

217

31.2

65.5

131

218

250

459

524

918

1049

218

62.4

131

262

437

499

918

1049

1835

2097

$0009

Bit 7

654321

Bit 0

Read:

Bit 7

654321

Bit 0

Write:

Reset:

00000000

= Unimplemented

Figure 10-3. Core Timer Counter Register (CTCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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