HC705JJ7GRSSLASHD datasheet(152/230 Pages) NXP

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Core Timer

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Core Timer

Each count of the timer counter register takes eight oscillator cycles or

four cycles of the internal bus. A timer overflow function at the eighth

counter stage allows a timer interrupt every 2048 oscillator clock cycles

or every 1024 internal bus cycles.

10.5 COP Watchdog

Four counter stages at the end of the core timer make up the computer

operating properly (COP) watchdog which can be enabled by the

COPEN bit in the MOR. The COP watchdog is a software error detection

system that automatically times out and resets the MCU if the COP

watchdog is not cleared periodically by a program sequence. Writing a

logic zero to COPC bit in the COP register clears the COP watchdog and

prevents a COP reset.

EPMSEC — EPROM Security1

The EPMSEC bit is a write-only security bit to protect the contents of

the user EPROM code stored in locations $0700–$1FFF.

OPT — Optional Features

The OPT bit enables two additional features: direct drive by

comparator outputs to port A; and voltage offset capability to sample

capacitor in analog subsystem.

1 = Optional features enabled

0 = Optional features disabled

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or

copying the EPROM/OTPROM difficult for unauthorized users.

$1FF0

Bit 7

654321

Bit 0

Read:

OPT

Write:

EPMSEC

COPC

Reset:

Unaffected by Reset

= Unimplemented

Figure 10-4. COP and Security Register (COPR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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