HC705JJ7GRSSLASHD datasheet(182/230 Pages) NXP

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EPROM/OTPROM

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

EPROM/OTPROM

SWPDI — Software Pulldown Inhibit

This EPROM bit inhibits software control of the port A and port B

pulldown devices.

1 = Software pulldown inhibited

0 = Software pulldown enabled

DELAY — Stop Startup Delay

This EPROM bit selects the number of bus cycles that must elapse

before bus activity begins following a restart from the stop mode.

1 = Startup delay is 4064 bus cycles

0 = Startup delay is 16 bus cycles

CAUTION:

The 16-cycle delay option will work properly in devices with the internal

low power oscillator or with a steady external clock source. Check

crystal/ceramic resonator specifications carefully before using the 16-

cycle delay option with a crystal or ceramic resonator.

OSCRES — Oscillator Resistor

This EPROM bit configures the on-chip oscillator an internal shunt

resistor.

1 = Oscillator configured with 2 M shunt resistor

0 = Oscillator configured without a shunt resistor

NOTE:

The optional oscillator resistor is NOT recommended for devices that

use an external RC oscillator. For such devices, this bit should be left

erased as a zero.

$1FF1

Bit 7

4321

Bit 0

Read:

SWPDI

DELAY

OSCRES

SWAIT

LVREN

PIRQ

LEVEL

COPEN

Write:

Reset:

Unaffected by Reset

Erased:

00000

Figure 13-2. Mask Option Register (MOR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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