HC705JJ7GRSSLASHD datasheet(118/230 Pages) NXP

118 / 230 page

Analog Subsystem

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Analog Subsystem

8.6 A/D Conversion Methods

The control bits in the ACR provide various options to charge or

discharge current through the PB0/AN0 pin in order to perform single-

slope A/D conversions using an external capacitor from the PB0/AN0 pin

to VSS as shown in Figure 8-7. The various A/D conversion triggering

options are given in Table 8-3.

Figure 8-7. Single-Slope A/D Conversion Method

The top three bits of the ACR control the charging and discharging

current into or out of the PB0/AN0 pin. These three bits will have no

effect on the PB0/AN0 pin if the ISEN enable bit is cleared. Any clearing

of the ISEN bit will immediately disable both the charge current source

and the discharge device. Since all these bits and the ISEN bit are

UNKNOWN VOLTAGE ON (–) INPUT

CHARGE TIME

TO MATCH UNKNOWN

DISCHARGE TIME

TO RESET CAPACITOR

VOLTAGE ON

CAPACITOR

CONNECTED

TO (+) INPUT

MAXIMUM CHARGE TIME

TO VDD –1.5 Vdc

VDD –1.5 Vdc

Cx VX

VDD

+ 5 V

RAMP

CAP

VSS

PB0/AN0

PB1/AN1

PB2/AN2

PB3/AN3

PB4/AN4

UNKNOWN

OR REFERENCE

MC68HC705JJ7

Charge Time =

MC68HC705JP7

SIGNALS

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D 数据表(PDF) 118 Page - NXP Semiconductors

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