HC705JJ7GRSSLASHD datasheet(119/230 Pages) NXP

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Analog Subsystem

A/D Conversion Methods

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Analog Subsystem

cleared when the device is reset, the MC68HC705JJ7/MC68HC705JP7

starts with the charge and discharge function disabled.

The length of time required to reach the maximum voltage to be

measured and the speed of the time counting mechanism will determine

the resolution of the reading. The time to ramp the external capacitor

voltage to match the maximum voltage is dependent on:

•

Charging current to external capacitor

•

Value of the external capacitor

•

Clock rate for timing function

•

Any prescaling of the clock to the timing function

•

Desired resolution

The charging behavior is described by the general equation:

tCHG = CEXT x VX / ICHG

Where:

tCHG = Charge time (seconds)

CEXT = Capacitance (µF)

= Unknown voltage (volts)

ICHG = Charge current (µA)

Since the MCU can measure time in a variety of ways, the resolution of

the conversion will depend on the length of the time keeping function and

its prescaling to the oscillator frequency (fOSC). Therefore the charge

time also equals:

tCHG = P x N / fOSC

Where:

= Prescaler value (

÷ 2, ÷ 4, ÷ 8, etc.)

= Number of counts during charge time

fOSC = Oscillator clock frequency (Hz)

NOTE:

Noise on the system ground or the external ramping capacitor can cause

the comparator to trip prematurely. Therefore in any given application it

is best to use the fastest possible ramp rate (shortest charge time).

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D 数据表(PDF) 119 Page - NXP Semiconductors

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