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HC705JJ7GRS/D 数据表(PDF) 124 Page - NXP Semiconductors |
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HC705JJ7GRS/D 数据表(HTML) 124 Page - NXP Semiconductors |
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124 / 230 page  Analog Subsystem General Release Specification MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 Analog Subsystem Figure 8-8. A/D Conversion — Full Manual Control (Mode 0) tDIS (MIN) tCHG x ICHG CEXT tCHG tDIS VX = tMAX VMAX CHG COMP2 0 TOF OCF ICF (MIN) VCAP tDIS VX 2 3 4 1 5 1 Point Action Software/Hardware Action Dependent Variable(s) 0 Begin initial discharge and select mode 0 by clearing the CHG, ATD2, and ATD1 control bits in the ACR. Software write Software 1VCAP falls to VSS. Wait out minimum tDIS time VMAX, IDIS, CEXT 2 Stop discharge and begin charge by setting CHG control bit in ACR. Software write Software 3 VCAP rises to VX and comparator 2 output trips, setting CPF2 and CMP2. Wait out tCHG time VX, ICHG, CEXT 4VCAP reaches VMAX. None VMAX, ICHG, CEXT 5 Begin next discharge by clearing the CHG control bit in the ACR. Reset CPF2 by writing a “1” to CPFR2. Software write Software Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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