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HC705JJ7GRS/D 数据表(PDF) 126 Page - NXP Semiconductors |
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HC705JJ7GRS/D 数据表(HTML) 126 Page - NXP Semiconductors |
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126 / 230 page  Analog Subsystem General Release Specification MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 Analog Subsystem Figure 8-10. A/D Conversion — TOF/ICF Control (Mode 2) tDIS (MIN) tCHG x ICHG CEXT tCHG tDIS VX = VMAX CHG COMP2 0 TOF OCF ICF (MIN) VCAP tDIS VX 1 2 3 1 2 (TCAP) Point Action Software/Hardware Action Dependent Variable(s) 0 Begin initial discharge and select mode 2 by clearing CHG and ATD1 and setting ATD2 in the ACR. Also set ICEN bit in ACR and IEDG bit in TCR. Software write Software 1VCAP falls to VSS. Wait out minimum tDIS time VMAX, IDIS, CEXT 2 Stop discharge and begin charge when the next TOF sets the CHG control bit in ACR. Timer TOF sets the CHG control bit in the ACR. Free-running timer counter overflow, fOSC 3 VCAP rises to VX and comparator 2 output trips, setting CPF2 and CMP2, which causes an ICF from the timer and clears the CHG control bit in ACR. Must clear CPF2 in order to trap next CPF2 flag. Wait out tCHG time Timer ICF clears the CHG control bit in the ACR. VX, ICHG, CEXT Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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