H8SX1663 datasheet(334/1158 Pages) RENESAS

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 282 of 1102

REJ09B0294-0100

Figure 6.81 shows the timing of setting SDRAM mode register.

RAS

CAS

CKE

High

Mode register setting

High

RD/

High

PALL

NOP

MRS

NOP

Precharge-sel

Address bus

Figure 6.81 Timing of Setting SDRAM Mode Register

6.11.15

SDRAM Interface and Single Address Transfer by DMAC

When fast-page mode (BE = 1) is set for the SDRAM space, either fast-page access or full access

can be selected, by the setting of bit DDS in DRAMCR, for the single address transfer by the

DMAC where the SDRAM space is specified as the transfer source or destination. At the same

time, the output timing of the

DACK and BS signals can be changed. When BE = 0, a full access

to the SDRAM space is performed with a single address transfer regardless of the setting of bit

DDS. However, the output timing of the

DACK and BS signals can be changed by the setting of

bit DDS.

The assertion timing of the

DACK signals can be changed by the bit DKC in BCR1.

The output timing of the

DACK signal can be independently set by the bits TRWL and CKSPE in

SDCR and bit DCK in BCR1 regardless of the setting of bit DDS.

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