H8SX1663 datasheet(37/1158 Pages) RENESAS

37 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xxxvii of x lii

Figure 12.4 Block Diagram of 8-Bit Timer Module (Unit 3) ..................................................... 609

Figure 12.5 Example of Pulse Output......................................................................................... 624

Figure 12.6 Example of Reset Input ...........................................................................................624

Figure 12.7 Count Timing for Internal Clock Input.................................................................... 625

Figure 12.8 Count Timing for External Clock Input .................................................................. 625

Figure 12.9 Timing of CMF Setting at Compare Match............................................................. 626

Figure 12.10 Timing of Toggled Timer Output at Compare Match A ....................................... 626

Figure 12.11 Timing of Counter Clear by Compare Match........................................................ 627

Figure 12.12 Timing of Clearance by External Reset (Rising Edge).......................................... 627

Figure 12.13 Timing of Clearance by External Reset (High Level) ........................................... 627

Figure 12.14 Timing of OVF Setting.......................................................................................... 628

Figure 12.15 Conflict between TCNT Write and Clear.............................................................. 631

Figure 12.16 Conflict between TCNT Write and Increment ...................................................... 632

Figure 12.17 Conflict between TCOR Write and Compare Match............................................. 632

Section 13 32K Timer (TM32K)

Figure 13.1 Block Diagram of TM32K ...................................................................................... 637

Figure 13.2 32K Timer Operation ..............................................................................................639

Section 14 Watchdog Timer (WDT)

Figure 14.1 Block Diagram of WDT .......................................................................................... 642

Figure 14.2 Operation in Watchdog Timer Mode....................................................................... 647

Figure 14.3 Operation in Interval Timer Mode........................................................................... 648

Figure 14.4 Writing to TCNT, TCSR, and RSTCSR.................................................................. 649

Figure 14.5 Conflict between TCNT Write and Increment ........................................................ 650

Figure 14.6 Circuit for System Reset by

WDTOVF Signal (Example)......................................651

Section 15 Serial Communication Interface (SCI, IrDA, CRC)

Figure 15.1 Block Diagram of SCI_0, 1, 2, and 4 ...................................................................... 656

Figure 15.2 Block Diagram of SCI_5 and SCI_6 ....................................................................... 657

Figure 15.3 Examples of Base Clock when Average Transfer Rate Is Selected (1) ................... 693

Figure 15.3 Examples of Base Clock when Average Transfer Rate Is Selected (2) ................... 694

Figure 15.3 Examples of Base Clock when Average Transfer Rate Is Selected (3) ................... 695

Figure 15.4 Example of Average Transfer Rate Setting when TMR Clock Is Input .................. 696

Figure 15.5 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits) ................................................. 698

Figure 15.6 Receive Data Sampling Timing in Asynchronous Mode ........................................ 700

Figure 15.7 Phase Relation between Output Clock and Transmit Data

(Asynchronous Mode) ............................................................................................ 701

Figure 15.8 Sample SCI Initialization Flowchart ....................................................................... 702

Figure 15.9 Example of Operation for Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 703

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