H8SX1663 datasheet(22/1158 Pages) RENESAS

22 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xxii of lii

15.6.4 Serial Data Reception (Clocked Synchronous Mode)

(SCI_0, 1, 2, and 4 only)....................................................................................... 719

15.6.5 Simultaneous Serial Data Transmission and Reception

(Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only)...................................... 720

15.7

Operation in Smart Card Interface Mode........................................................................... 722

15.7.1 Sample Connection ............................................................................................... 722

15.7.2 Data Format (Except in Block Transfer Mode) .................................................... 723

15.7.3 Block Transfer Mode ............................................................................................ 724

15.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 725

15.7.5 Initialization.......................................................................................................... 726

15.7.6 Data Transmission (Except in Block Transfer Mode) .......................................... 727

15.7.7 Serial Data Reception (Except in Block Transfer Mode) ..................................... 730

15.7.8 Clock Output Control............................................................................................ 731

15.8

IrDA Operation .................................................................................................................. 733

15.9

Interrupt Sources................................................................................................................ 736

15.9.1 Interrupts in Normal Serial Communication Interface Mode ............................... 736

15.9.2 Interrupts in Smart Card Interface Mode .............................................................. 737

15.10 Usage Notes ....................................................................................................................... 739

15.10.1 Module Stop State Setting .................................................................................... 739

15.10.2 Break Detection and Processing ........................................................................... 739

15.10.3 Mark State and Break Detection ........................................................................... 739

15.10.4 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only) ..................................................................... 739

15.10.5 Relation between Writing to TDR and TDRE Flag .............................................. 740

15.10.6 Restrictions on Using DTC or DMAC.................................................................. 740

15.10.7 SCI Operations during Power-Down State ........................................................... 741

15.11 CRC Operation Circuit ...................................................................................................... 744

15.11.1 Features................................................................................................................. 744

15.11.2 Register Descriptions ............................................................................................ 745

15.11.3 CRC Operation Circuit Operation ........................................................................ 747

15.11.4 Note on CRC Operation Circuit............................................................................ 750

Section 16 USB Function Module (USB) ......................................................... 751

16.1

Features.............................................................................................................................. 751

16.2

Input/Output Pins ............................................................................................................... 752

16.3

Register Descriptions ......................................................................................................... 753

16.3.1 Interrupt Flag Register 0 (IFR0) ........................................................................... 754

16.3.2 Interrupt Flag Register 1 (IFR1) ........................................................................... 756

16.3.3 Interrupt Flag Register 2 (IFR2) ........................................................................... 757

16.3.4 Interrupt Select Register 0 (ISR0)......................................................................... 759

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