H8SX1663 datasheet(15/1158 Pages) RENESAS

15 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xv of lii

7.2

Input/Output Pins ............................................................................................................... 320

7.3

Register Descriptions ......................................................................................................... 321

7.3.1

DMA Source Address Register (DSAR)............................................................... 322

7.3.2

DMA Destination Address Register (DDAR)....................................................... 323

7.3.3

DMA Offset Register (DOFR).............................................................................. 324

7.3.4

DMA Transfer Count Register (DTCR) ............................................................... 325

7.3.5

DMA Block Size Register (DBSR) ...................................................................... 326

7.3.6

DMA Mode Control Register (DMDR)................................................................ 327

7.3.7

DMA Address Control Register (DACR) ............................................................. 336

7.3.8

DMA Module Request Select Register (DMRSR) ............................................... 342

7.4

Transfer Modes .................................................................................................................. 342

7.5

Operations .......................................................................................................................... 343

7.5.1

Address Modes ..................................................................................................... 343

7.5.2

Transfer Modes ..................................................................................................... 347

7.5.3

Activation Sources ................................................................................................ 352

7.5.4

Bus Access Modes ................................................................................................ 354

7.5.5

Extended Repeat Area Function ........................................................................... 356

7.5.6

Address Update Function using Offset ................................................................. 359

7.5.7

7.5.8

Priority of Channels .............................................................................................. 368

7.5.9

DMA Basic Bus Cycle.......................................................................................... 370

7.5.10 Bus Cycles in Dual Address Mode ....................................................................... 371

7.5.11 Bus Cycles in Single Address Mode..................................................................... 380

7.6

DMA Transfer End ............................................................................................................ 385

7.7

Relationship among DMAC and Other Bus Masters ......................................................... 388

7.7.1

CPU Priority Control Function Over DMAC ....................................................... 388

7.7.2

Bus Arbitration among DMAC and Other Bus Masters ....................................... 389

7.8

Interrupt Sources................................................................................................................ 390

7.9

Notes on Usage .................................................................................................................. 393

Section 8 Data Transfer Controller (DTC) ........................................................395

8.1

Features .............................................................................................................................. 395

8.2

Register Descriptions ......................................................................................................... 397

8.2.1

DTC Mode Register A (MRA) ............................................................................. 398

8.2.2

DTC Mode Register B (MRB).............................................................................. 399

8.2.3

DTC Source Address Register (SAR)................................................................... 400

8.2.4

DTC Destination Address Register (DAR)........................................................... 401

8.2.5

DTC Transfer Count Register A (CRA) ............................................................... 401

8.2.6

DTC Transfer Count Register B (CRB)................................................................ 402

H8SX1663 数据表(PDF) 15 Page - Renesas Technology Corp

H8SX1663 数据表(HTML) 15 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载