H8SX1663 datasheet(65/1158 Pages) RENESAS

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Section 1 Overview

Rev.1.00 Jun. 07, 2006 Page 13 of 1102

REJ09B0294-0100

Classification

Abbreviation

Pin No.

(FP-144LV) I/O

Description

Bus control

LUCAS/DQMLU

116

Output

•

Upper-column address strobe signal for

16-bit DRAM interface space.

• Upper-data mask enable signal for 16-bit

synchronous DRAM interface space.

LLCAS/DQMLL

117

Output

•

Lower-column address strobe signal for

16-bit DRAM interface space

•

Column address strobe signal for 8-bit

DRAM interface space.

•

Lower-data mask enable signal for 16-bit

synchronous DRAM interface space.

•

Data mask enable signal for 8-bit

synchronous DRAM interface space

Interrupt

NMI

Input

Non-maskable interrupt request signal. When

this pin is not in use, this signal must be fixed

high.

IRQ11-A/IRQ11-B

IRQ10-A/IRQ10-B

IRQ9-A/IRQ9-B

IRQ8-A/IRQ8-B

IRQ7-A/IRQ7-B

IRQ6-A/IRQ6-B

IRQ5-A/IRQ5-B

IRQ4-A/IRQ4-B

IRQ3-A/IRQ3-B

IRQ2-A/IRQ2-B

IRQ1-A/IRQ1-B

IRQ0-A/IRQ0-B

53/111

52/109

51/108

49/107

101/128

100/127

94/126

93/124

87/122

86/120

85/119

84/118

Input

Maskable interrupt request signal.

DMA controller

(DMAC)

DREQ0-A/DREQ0-B

DREQ1-A/DREQ1-B

DREQ2

DREQ3

84/56

93/62

107

111

Input

Requests DMAC activation.

DACK0-A/DACK0-B

DACK1-A/DACK1-B

DACK2

DACK3

86/58

100/104

109

114

Output DMAC single address transfer acknowledge

signal.

TEND0-A/TEND0-B

TEND1-A/TEND1-B

TEND2

TEND3

85/57

94/63

108

113

Output Indicates DMAC data transfer end.

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