H8SX1663 datasheet(29/1158 Pages) RENESAS

29 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xxix of x lii

Figures

Section 1 Overview

Figure 1.1 Block Diagram .............................................................................................................. 2

Figure 1.2 Pin Assignments ............................................................................................................ 3

Section 2 CPU

Figure 2.1 CPU Operating Modes ................................................................................................23

Figure 2.2 Exception Vector Table (Normal Mode)..................................................................... 24

Figure 2.3 Stack Structure (Normal Mode) .................................................................................. 24

Figure 2.4 Exception Vector Table (Middle and Advanced Modes) ............................................ 26

Figure 2.5 Stack Structure (Middle and Advanced Modes).......................................................... 27

Figure 2.6 Exception Vector Table (Maximum Modes) ............................................................... 28

Figure 2.7 Stack Structure (Maximum Mode) .............................................................................. 28

Figure 2.8 Memory Map............................................................................................................... 29

Figure 2.9 CPU Registers ............................................................................................................. 30

Figure 2.10 Usage of General Registers .......................................................................................31

Figure 2.11 Stack.......................................................................................................................... 32

Figure 2.12 General Register Data Formats.................................................................................. 36

Figure 2.13 Memory Data Formats...............................................................................................37

Figure 2.14 Instruction Formats.................................................................................................... 54

Figure 2.15 Branch Address Specification in Memory Indirect Mode ......................................... 60

Figure 2.16 State Transitions ........................................................................................................ 64

Section 3 MCU Operating Modes

Figure 3.1 Address Map in Each Operating Mode of H8SX/1663 (1).......................................... 73

Figure 3.1 Address Map in Each Operating Mode of H8SX/1663 (2).......................................... 74

Figure 3.2 Address Map in Each Operating Mode of H8SX/1664 (1).......................................... 75

Figure 3.2 Address Map in Each Operating Mode of H8SX/1664 (2).......................................... 76

Section 4 Exception Handling

Figure 4.1 Reset Sequence (On-chip ROM Enabled Advanced Mode)........................................ 81

Figure 4.2 Reset Sequence

(16-Bit External Access in On-chip ROM Disabled Advanced Mode) ...................... 82

Figure 4.3 Stack Status after Exception Handling ........................................................................ 90

Figure 4.4 Operation when SP Value is Odd ................................................................................ 91

Section 5 Interrupt Controller

Figure 5.1 Block Diagram of Interrupt Controller ........................................................................ 94

Figure 5.2 Block Diagram of Interrupts IRQn............................................................................ 110

Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0... 117

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