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H8SX1663 数据表(PDF) 95 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 95 Page - Renesas Technology Corp |
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95 / 1158 page ![]() Section 2 CPU Rev.1.00 Jun. 07, 2006 Page 43 of 1102 REJ09B0294-0100 Table 2.2 Combinations of Instructions and Addressing Modes (2) Addressing Mode Classifi- cation Instruction Size @ERn @(d,PC) @(RnL. B/Rn.W/ ERn.L, PC) @aa:24 @ aa:32 @@ aa:8 @@vec: 7 — Branch BRA/BS, BRA/BC — O BSR/BS, BSR/BC — O Bcc — O BRA — O O BRA/S — O* JMP — O O O O O BSR — O JSR — O O O O O RTS, RTS/L — O TRAPA — O System control RTE, RTE/L — O [Legend] d: d:8 or d:16 Note: * Only @(d:8, PC) is available. |
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