H8SX1663 datasheet(19/1158 Pages) RENESAS

19 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xix of lii

11.3.2 Output Data Registers H, L (PODRH, PODRL)................................................... 587

11.3.3 Next Data Registers H, L (NDRH, NDRL) .......................................................... 588

11.3.4 PPG Output Control Register (PCR) .................................................................... 591

11.3.5 PPG Output Mode Register (PMR) ...................................................................... 592

11.4

Operation ........................................................................................................................... 594

11.4.1 Output Timing....................................................................................................... 594

11.4.2 Sample Setup Procedure for Normal Pulse Output............................................... 595

11.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output)................ 596

11.4.4 Non-Overlapping Pulse Output............................................................................. 597

11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output ............................... 599

11.4.6 Example of Non-Overlapping Pulse Output (Example of

4-Phase Complementary Non-Overlapping Pulse Output) ................................... 600

11.4.7 Inverted Pulse Output ........................................................................................... 602

11.4.8 Pulse Output Triggered by Input Capture ............................................................. 603

11.5

Usage Notes ....................................................................................................................... 604

11.5.1 Module Stop State Setting .................................................................................... 604

11.5.2 Operation of Pulse Output Pins............................................................................. 604

Section 12 8-Bit Timers (TMR).........................................................................605

12.1

Features .............................................................................................................................. 605

12.2

Input/Output Pins ............................................................................................................... 610

12.3

Register Descriptions ......................................................................................................... 611

12.3.1 Timer Counter (TCNT)......................................................................................... 613

12.3.2 Time Constant Register A (TCORA).................................................................... 613

12.3.3 Time Constant Register B (TCORB) .................................................................... 614

12.3.4 Timer Control Register (TCR).............................................................................. 614

12.3.5 Timer Counter Control Register (TCCR) ............................................................. 616

12.3.6 Timer Control/Status Register (TCSR)................................................................. 619

12.4

Operation ........................................................................................................................... 623

12.4.1 Pulse Output.......................................................................................................... 623

12.4.2 Reset Input ............................................................................................................ 624

12.5

Operation Timing............................................................................................................... 625

12.5.1 TCNT Count Timing............................................................................................. 625

12.5.2 Timing of CMFA and CMFB Setting at Compare Match..................................... 626

12.5.3 Timing of Timer Output at Compare Match ......................................................... 626

12.5.4 Timing of Counter Clear by Compare Match ....................................................... 627

12.5.5 Timing of TCNT External Reset........................................................................... 627

12.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 628

12.6

Operation with Cascaded Connection ................................................................................ 628

12.6.1 16-Bit Counter Mode ............................................................................................ 628

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