H8SX1663 datasheet(39/1158 Pages) RENESAS

39 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xxxix of x lii

Figure 15.41 Port Pin States during Software Standby Mode Transition

(Internal Clock, Clocked Synchronous Transmission)

(Setting is Prohibited in SCI_5 and SCI_6) .......................................................... 743

Figure 15.42 Sample Flowchart for Software Standby Mode Transition during Reception....... 743

Figure 15.43 Block Diagram of CRC Operation Circuit ............................................................ 744

Figure 15.44 LSB-First Data Transmission ................................................................................ 747

Figure 15.45 MSB-First Data Transmission ............................................................................... 747

Figure 15.46 LSB-First Data Reception ..................................................................................... 748

Figure 15.47 MSB-First Data Reception .................................................................................... 749

Figure 15.48 LSB-First and MSB-First Transmit Data .............................................................. 750

Section 16 USB Function Module (USB)

Figure 16.1 Block Diagram of USB ........................................................................................... 752

Figure 16.2 Cable Connection Operation ................................................................................... 788

Figure 16.3 Cable Disconnection Operation............................................................................... 789

Figure 16.4 Suspend Operation .................................................................................................. 790

Figure 16.5 Resume Operation from Up-Stream ........................................................................ 791

Figure 16.6 Flow of Transition to and Canceling Software Standby Mode................................ 792

Figure 16.7 Timing of Transition to and Canceling Software Standby Mode ............................ 793

Figure 16.8 Remote-Wakeup...................................................................................................... 794

Figure 16.9 Transfer Stages in Control Transfer ........................................................................ 795

Figure 16.10 Setup Stage Operation ...........................................................................................796

Figure 16.11 Data Stage (Control-In) Operation ........................................................................ 797

Figure 16.12 Data Stage (Control-Out) Operation...................................................................... 798

Figure 16.13 Status Stage (Control-In) Operation ...................................................................... 799

Figure 16.14 Status Stage (Control-Out) Operation ................................................................... 800

Figure 16.15 EP1 Bulk-Out Transfer Operation......................................................................... 801

Figure 16.16 EP2 Bulk-In Transfer Operation............................................................................ 802

Figure 16.17 Operation of EP3 Interrupt-In Transfer ................................................................. 804

Figure 16.18 Forcible Stall by Application................................................................................. 807

Figure 16.19 Automatic Stall by USB Function Module............................................................ 808

Figure 16.20 RDFN Bit Operation for EP1 ................................................................................ 809

Figure 16.21 PKTE Bit Operation for EP2................................................................................. 810

Figure 16.22 Example of Circuitry in Bus Power Mode ............................................................ 811

Figure 16.23 Example of Circuitry in Self Power Mode ............................................................ 812

Figure 16.24 TR Interrupt Flag Set Timing ................................................................................ 814

Section 17 I2C Bus Interface2 (IIC2)

Figure 17.1 Block Diagram of I2C Bus Interface 2..................................................................... 818

Figure 17.2 Connections to the External Circuit by the I/O Pins................................................ 819

Figure 17.3 I2C Bus Formats ...................................................................................................... 833

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