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H8SX1663 数据表(PDF) 61 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 61 Page - Renesas Technology Corp |
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61 / 1158 page ![]() Section 1 Overview Rev.1.00 Jun. 07, 2006 Page 9 of 1102 REJ09B0294-0100 1.3.3 Pin Functions Table 1.2 Pin Functions Classification Abbreviation Pin No. (FP-144LV) I/O Description Power supply V CC 6, 25, 50, 64, 74, 99, 143 Input Power supply pins. Connect to the system power supply. V CL 92 Input Connect this pin to V SS via a 0.1-µF capacitor. (The capacitor should be placed close to the pin.) V SS 4, 16, 23, 32, 48, 69, 79, 88, 96, 103, 141 Input Ground pins. Connect to the system power supply (0 V). PLLV CC 110 Input Power supply pin for the PLL circuits. Connect to the system power supply. PLLV SS 112 Input Ground pin for the PLL circuits. DrVCC 42 Input Power supply pin for USB on-chip transceiver. Connect to the system power supply. DrVSS 45 Input Ground pin for USB on-chip transceiver Clock XTAL 97 Input EXTAL 98 Input Pins for a crystal resonator. External clock can be input to the EXTAL pin. For a connection example, see section 22, Clock Pulse Generator. OSC1 90 Input Connects the 32.768-kHz crystal resonator. OSC2 89 Input Connect the 32.768-kHz crystal resonator. B φ 142 Output Outputs the system clock for external devices. SDRAM φ 5 Output Connects to the CLK pin of synchronous DRAM when synchronous DRAM is connected. For details, see section 6, Bus Controller (BSC). Operating mode control MD3 MD2 MD1 MD0 133 7 129 115 Input Pins for setting the operating mode. The signal levels of these pins must not be changed during operation. MD_CLK 47 Input Pin for changing the multiplication ratio of the clock pulse generator. The signal levels of this pin must not be changed during operation. |
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