H8SX1663 datasheet(87/1158 Pages) RENESAS

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Section 2 CPU

Rev.1.00 Jun. 07, 2006 Page 35 of 1102

REJ09B0294-0100

2.5.5

Vector Base Register (VBR)

VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are

read as 0s. This register is a base address of the vector area for exception handlings other than a

reset and a CPU address error (extended memory indirect is also out of the target). The initial

value is H'00000000. The VBR contents are changed with the LDC and STC instructions.

2.5.6

Short Address Base Register (SBR)

SBR is a 32-bit register in which the upper 24 bits are valid. The lower eight bits are read as 0s. In

8-bit absolute address addressing mode (@aa:8), this register is used as the upper address. The

initial value is H'FFFFFF00. The SBR contents are changed with the LDC and STC instructions.

2.5.7

Multiply-Accumulate Register (MAC)

MAC is a 64-bit register that stores the results of multiply-and-accumulate operations. It consists

of two 32-bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the

upper bits are sign extended. The MAC contents are changed with the MAC, CLRMAC, LDMAC,

and STMAC instructions.

2.5.8

Initial Values of CPU Registers

Reset exception handling loads the start address from the vector table into the PC, clears the T bit

in EXR to 0, and sets the I bits in CCR and EXR to 1. The general registers, MAC, and the other

bits in CCR are not initialized. In particular, the initial value of the stack pointer (ER7) is

undefined. The SP should therefore be initialized using an MOV.L instruction executed

immediately after a reset.

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