H8SX1663 datasheet(12/1158 Pages) RENESAS

12 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xii of lii

5.8.4

Interrupts during Execution of EEPMOV Instruction........................................... 129

5.8.5

Interrupts during Execution of MOVMD and MOVSD Instructions.................... 129

5.8.6

Interrupts of Peripheral Modules .......................................................................... 130

Section 6 Bus Controller (BSC) ........................................................................ 131

6.1

Features.............................................................................................................................. 131

6.2

Register Descriptions ......................................................................................................... 134

6.2.1

Bus Width Control Register (ABWCR)................................................................ 135

6.2.2

Access State Control Register (ASTCR) .............................................................. 136

6.2.3

Wait Control Registers A and B (WTCRA, WTCRB) ......................................... 137

6.2.4

Read Strobe Timing Control Register (RDNCR) ................................................. 142

6.2.5

CS Assertion Period Control Registers (CSACR) ................................................ 143

6.2.6

Idle Control Register (IDLCR) ............................................................................. 146

6.2.7

Bus Control Register 1 (BCR1) ............................................................................ 148

6.2.8

Bus Control Register 2 (BCR2) ............................................................................ 150

6.2.9

Endian Control Register (ENDIANCR) ............................................................... 151

6.2.10 SRAM Mode Control Register (SRAMCR) ......................................................... 152

6.2.11 Burst ROM Interface Control Register (BROMCR) ............................................ 153

6.2.12 Address/Data Multiplexed I/O Control Register (MPXCR) ................................. 155

6.2.13 DRAM Control Register (DRAMCR) .................................................................. 156

6.2.14 DRAM Access Control Register (DRACCR)....................................................... 160

6.2.15 Synchronous DRAM Control Register (SDCR) ................................................... 162

6.2.16 Refresh Control Register (REFCR) ...................................................................... 163

6.2.17 Refresh Timer Counter (RTCNT)......................................................................... 167

6.2.18 Refresh Time Constant Register (RTCOR) .......................................................... 167

6.3

Bus Configuration.............................................................................................................. 168

6.4

Multi-Clock Function and Number of Access Cycles ....................................................... 169

6.5

External Bus....................................................................................................................... 173

6.5.1

Input/Output Pins.................................................................................................. 173

6.5.2

Area Division........................................................................................................ 177

6.5.3

Chip Select Signals ............................................................................................... 178

6.5.4

External Bus Interface .......................................................................................... 179

6.5.5

Area and External Bus Interface ........................................................................... 184

6.5.6

Endian and Data Alignment.................................................................................. 189

6.6

Basic Bus Interface ............................................................................................................ 192

6.6.1

Data Bus ............................................................................................................... 192

6.6.2

I/O Pins Used for Basic Bus Interface .................................................................. 192

6.6.3

Basic Timing......................................................................................................... 193

6.6.4

Wait Control ......................................................................................................... 199

6.6.5

Read Strobe (

RD) Timing..................................................................................... 201

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