H8SX1663 datasheet(47/1158 Pages) RENESAS

47 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xlvii of lii

Table 6.31

Pin States in Idle Cycle ......................................................................................... 303

Table 6.32

Pin States in Bus Released State ........................................................................... 305

Table 6.33

Number of Access Cycles for On-Chip Memory Spaces...................................... 308

Table 6.34

Number of Access Cycles for Registers of On-Chip Peripheral Modules ............ 308

Section 7 DMA Controller (DMAC)

Table 7.1

Pin Configuration.................................................................................................. 320

Table 7.2

Data Access Size, Valid Bits, and Settable Size ................................................... 327

Table 7.3

Settings and Areas of Extended Repeat Area ....................................................... 341

Table 7.4

Transfer Modes ..................................................................................................... 342

Table 7.5

List of On-chip module interrupts to DMAC........................................................ 353

Table 7.6

Priority among DMAC Channels.......................................................................... 368

Table 7.7

Interrupt Sources and Priority............................................................................... 390

Section 8 Data Transfer Controller (DTC)

Table 8.1

Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs............... 407

Table 8.2

DTC Transfer Modes ............................................................................................ 409

Table 8.3

Chain Transfer Conditions.................................................................................... 411

Table 8.4

Number of Bus Cycle Divisions and Access Size................................................. 411

Table 8.5

Transfer Information Writeback Skip Condition

and Writeback Skipped Registers ......................................................................... 414

Table 8.6

Table 8.7

Table 8.8

Table 8.9

DTC Execution Status........................................................................................... 421

Table 8.10

Number of Cycles Required for Each Execution State ......................................... 422

Section 9 I/O Ports

Table 9.1

Port Functions ....................................................................................................... 429

Table 9.2

Table 9.3

Startup Mode and Initial Value............................................................................. 437

Table 9.4

Input Pull-Up MOS State...................................................................................... 440

Table 9.5

Available Output Signals and Settings in Each Port............................................. 476

Section 10 16-Bit Timer Pulse Unit (TPU)

Table 10.1

TPU Functions ...................................................................................................... 498

Table 10.2

Pin Configuration.................................................................................................. 501

Table 10.3

CCLR2 to CCLR0 (Channels 0 and 3) ................................................................. 505

Table 10.4

CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) ........................................................ 505

Table 10.5

Input Clock Edge Selection .................................................................................. 506

Table 10.6

TPSC2 to TPSC0 (Channel 0) .............................................................................. 506

Table 10.7

TPSC2 to TPSC0 (Channel 1) .............................................................................. 506

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