H8SX1663 datasheet(46/1158 Pages) RENESAS

46 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xlvi of lii

Section 5 Interrupt Controller

Table 5.1

Pin Configuration.................................................................................................... 95

Table 5.2

Interrupt Sources, Vector Address Offsets, and Interrupt Priority........................ 111

Table 5.3

Interrupt Control Modes ....................................................................................... 116

Table 5.4

Interrupt Response Times ..................................................................................... 121

Table 5.5

Number of Execution States in Interrupt Handling Routine ................................. 122

Table 5.6

Interrupt Source Selection and Clear Control ....................................................... 124

Table 5.7

CPU Priority Control ............................................................................................ 126

Table 5.8

Example of Priority Control Function Setting and Control State ......................... 127

Section 6 Bus Controller (BSC)

Table 6.1

Synchronization Clocks and Their Corresponding Functions............................... 169

Table 6.2

Pin Configuration.................................................................................................. 173

Table 6.3

Pin Functions in Each Interface ............................................................................ 176

Table 6.4

Interface Names and Area Names......................................................................... 179

Table 6.5

Areas Specifiable for Each Interface .................................................................... 180

Table 6.6

Number of Access Cycles..................................................................................... 183

Table 6.7

Area 0 External Interface...................................................................................... 184

Table 6.8

Area 1 External Interface...................................................................................... 185

Table 6.9

Area 2 External Interface...................................................................................... 185

Table 6.10

Area 3 External Interface...................................................................................... 186

Table 6.11

Area 4 External Interface...................................................................................... 186

Table 6.12

Area 5 External Interface...................................................................................... 187

Table 6.13

Area 6 External Interface...................................................................................... 188

Table 6.14

Area 7 External Interface...................................................................................... 188

Table 6.15

I/O Pins for Basic Bus Interface ........................................................................... 192

Table 6.16

I/O Pins for Byte Control SRAM Interface .......................................................... 206

Table 6.17

I/O Pins Used for Burst ROM Interface................................................................ 214

Table 6.18

Address/Data Multiplex........................................................................................ 218

Table 6.19

I/O Pins for Address/Data Multiplexed I/O Interface ........................................... 219

Table 6.20

Relationship Among DRAME and DTYPE and Area 2 Interfaces ...................... 228

Table 6.21

Relationship Among MXC1 and MXC0 and Shifted Bit Count........................... 228

Table 6.22

I/O Pins for DRAM Interface ............................................................................... 229

Table 6.23

Pin States during DRAM Refresh Cycle............................................................... 248

Table 6.24

Relationship among DRAME and DTYPE and Area 2 Interfaces ....................... 254

Table 6.25

Relationship Among MXC1 and MXC0 and Shifted Bit Count........................... 255

Table 6.26

I/O Pins for SDRAM Interface ............................................................................. 256

Table 6.27

CAS Latency Setting ............................................................................................ 259

Table 6.28

Number of Idle Cycle Insertion Selection in Each Area....................................... 292

Table 6.29

Number of Idle Cycles Inserted ............................................................................ 292

Table 6.30

Idle Cycles in Mixed Accesses to Normal Space and DRAM/SDRAM Space .... 302

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