H8SX1663 datasheet(42/1158 Pages) RENESAS

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Rev.1.00 Jun. 07, 2006 Page xlii of lii

Figure 23.7 When Canceling Factor Interrupt is Generated Immediately before SLEEP

Instruction Execution (Sleep Instruction Exception Handling Initiated) ................ 991

Section 25 Electrical Characteristics

Figure 25.1 Output Load Circuit .............................................................................................. 1043

Figure 25.2 External Bus Clock Timing................................................................................... 1044

Figure 25.3 Oscillation Settling Timing after Software Standby Mode ................................... 1044

Figure 25.4 Oscillation Settling Timing ................................................................................... 1045

Figure 25.5 External Input Clock Timing................................................................................. 1045

Figure 25.6 Reset Input Timing................................................................................................ 1046

Figure 25.7 Interrupt Input Timing........................................................................................... 1047

Figure 25.8 Basic Bus Timing: Two-State Access ................................................................... 1052

Figure 25.9 Basic Bus Timing: Three-State Access ................................................................. 1053

Figure 25.10 Basic Bus Timing: Three-State Access, One Wait.............................................. 1054

Figure 25.11 Basic Bus Timing: Two-State Access (

CS Assertion Period Extended) ............. 1055

Figure 25.12 Basic Bus Timing: Three-State Access (

CS Assertion Period Extended) ........... 1056

Figure 25.13 Byte Control SRAM: Two-State Read/Write Access.......................................... 1057

Figure 25.14 Byte Control SRAM: Three-State Read/Write Access........................................ 1058

Figure 25.15 Burst ROM Access Timing: One-State Burst Access ......................................... 1059

Figure 25.16 Burst ROM Access Timing: Two-State Burst Access......................................... 1060

Figure 25.17 Address/Data Multiplexed Access Timing (No Wait)

(Basic, Four-State Access).................................................................................. 1061

Figure 25.18 Address/Data Multiplexed Access Timing (Wait Control)

(Address Cycle Program Wait

× 1 + Data Cycle Program Wait × 1

+ Data Cycle Pin Wait

× 1)................................................................................ 1062

Figure 25.19 DRAM Access Timing: Two-State Access ......................................................... 1063

Figure 25.20 DRAM Access Timing: Two-State Access, One Wait........................................ 1064

Figure 25.21 DRAM Access Timing: Two-State Burst Access ............................................... 1065

Figure 25.22 DRAM Access Timing: Three-State Access (RAST = 1) ................................... 1066

Figure 25.23 DRAM Access Timing: Three-State Access, One Wait...................................... 1067

Figure 25.24 DRAM Access Timing: Three-State Burst Access ............................................. 1068

Figure 25.25 CAS Before RAS Refresh Timing ...................................................................... 1069

Figure 25.26 CAS Before RAS Refresh Timing (Wait Cycle Inserted) ................................... 1069

Figure 25.27 Self-Refresh Timing (After Leaving Software Standby: RAST = 0) .................. 1069

Figure 25.28 Self-Refresh Timing (After Leaving Software Standby: RAST = 1) .................. 1070

Figure 25.29 Synchronous DRAM Basic Read Access Timing (CAS Latency 2) ................... 1070

Figure 25.30 Synchronous DRAM Basic Write Access Timing (CAS Latency 2) .................. 1071

Figure 25.31 Extended Read Data Cycle (CAS Latency 2)...................................................... 1072

Figure 25.32 Synchronous DRAM Self-Refresh Timing ......................................................... 1073

Figure 25.33 External Bus Release Timing .............................................................................. 1073

Figure 25.34 External Bus Request Output Timing.................................................................. 1074

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