H8SX1663 datasheet(36/1158 Pages) RENESAS

36 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xxxvi of lii

Figure 10.32 Output Compare Output Timing ........................................................................... 567

Figure 10.33 Input Capture Input Signal Timing........................................................................ 567

Figure 10.34 Counter Clear Timing (Compare Match) .............................................................. 568

Figure 10.35 Counter Clear Timing (Input Capture) .................................................................. 568

Figure 10.36 Buffer Operation Timing (Compare Match).......................................................... 569

Figure 10.37 Buffer Operation Timing (Input Capture) ............................................................. 569

Figure 10.38 TGI Interrupt Timing (Compare Match) ............................................................... 570

Figure 10.39 TGI Interrupt Timing (Input Capture) ................................................................... 570

Figure 10.40 TCIV Interrupt Setting Timing.............................................................................. 571

Figure 10.41 TCIU Interrupt Setting Timing.............................................................................. 571

Figure 10.42 Timing for Status Flag Clearing by CPU .............................................................. 572

Figure 10.43 Timing for Status Flag Clearing by DTC or DMAC Activation (1)...................... 573

Figure 10.44 Timing for Status Flag Clearing by DTC or DMAC Activation (2)...................... 573

Figure 10.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................ 574

Figure 10.46 Conflict between TCNT Write and Clear Operations ........................................... 575

Figure 10.47 Conflict between TCNT Write and Increment Operations.................................... 576

Figure 10.48 Conflict between TGR Write and Compare Match ............................................... 576

Figure 10.49 Conflict between Buffer Register Write and Compare Match .............................. 577

Figure 10.50 Conflict between TGR Read and Input Capture.................................................... 578

Figure 10.51 Conflict between TGR Write and Input Capture................................................... 579

Figure 10.52 Conflict between Buffer Register Write and Input Capture .................................. 580

Figure 10.53 Conflict between Overflow and Counter Clearing ................................................ 581

Figure 10.54 Conflict between TCNT Write and Overflow ....................................................... 582

Section 11 Programmable Pulse Generator (PPG)

Figure 11.1 Block Diagram of PPG............................................................................................ 583

Figure 11.2 Schematic Diagram of PPG..................................................................................... 594

Figure 11.3 Timing of Transfer and Output of NDR Contents (Example) ................................. 594

Figure 11.4 Setup Procedure for Normal Pulse Output (Example) ............................................ 595

Figure 11.5 Normal Pulse Output Example (5-Phase Pulse Output) .......................................... 596

Figure 11.6 Non-Overlapping Pulse Output ............................................................................... 597

Figure 11.7 Non-Overlapping Operation and NDR Write Timing ............................................. 598

Figure 11.8 Setup Procedure for Non-Overlapping Pulse Output (Example)............................. 599

Figure 11.9 Non-Overlapping Pulse Output Example (4-Phase Complementary) ..................... 600

Figure 11.10 Inverted Pulse Output (Example) .......................................................................... 602

Figure 11.11 Pulse Output Triggered by Input Capture (Example)............................................ 603

Section 12 8-Bit Timers (TMR)

Figure 12.1 Block Diagram of 8-Bit Timer Module (Unit 0) ..................................................... 606

Figure 12.2 Block Diagram of 8-Bit Timer Module (Unit 1) ..................................................... 607

Figure 12.3 Block Diagram of 8-Bit Timer Module (Unit 2) ..................................................... 608

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