H8SX1663 datasheet(25/1158 Pages) RENESAS

25 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xxv of lii

18.3

Register Descriptions ......................................................................................................... 851

18.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 852

18.3.2 A/D Control/Status Register (ADCSR) ................................................................ 853

18.3.3 A/D Control Register (ADCR) ............................................................................. 855

18.4

Operation ........................................................................................................................... 856

18.4.1 Single Mode.......................................................................................................... 856

18.4.2 Scan Mode ............................................................................................................ 857

18.4.3 Input Sampling and A/D Conversion Time .......................................................... 859

18.4.4 External Trigger Input Timing.............................................................................. 860

18.5

Interrupt Source ................................................................................................................. 861

18.6

A/D Conversion Accuracy Definitions .............................................................................. 861

18.7

Usage Notes ....................................................................................................................... 863

18.7.1 Module Stop State Setting .................................................................................... 863

18.7.2 Permissible Signal Source Impedance .................................................................. 863

18.7.3 Influences on Absolute Accuracy ......................................................................... 863

18.7.4 Setting Range of Analog Power Supply and Other Pins ....................................... 864

18.7.5 Notes on Board Design ......................................................................................... 864

18.7.6 Notes on Noise Countermeasures ......................................................................... 864

18.7.7 A/D Input Hold Function in Software Standby Mode .......................................... 865

Section 19 D/A Converter..................................................................................867

19.1

Features .............................................................................................................................. 867

19.2

Input/Output Pins ............................................................................................................... 868

19.3

Register Descriptions ......................................................................................................... 868

19.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)............................................. 868

19.3.2 D/A Control Register 01 (DACR01) .................................................................... 869

19.4

Operation ........................................................................................................................... 871

19.5

Usage Notes ....................................................................................................................... 872

19.5.1 Module Stop State Setting .................................................................................... 872

19.5.2 D/A Output Hold Function in Software Standby Mode........................................ 872

Section 20 RAM ................................................................................................873

Section 21 Flash Memory (0.18-

µm F-ZTAT Version) ....................................875

21.1

Features .............................................................................................................................. 875

21.2

Mode Transition Diagram.................................................................................................. 877

21.3

Block Structure .................................................................................................................. 879

21.3.1 Block Diagram of H8SX/1663.............................................................................. 879

21.3.2 Block Diagram of H8SX/1664.............................................................................. 880

21.4

Programming/Erasing Interface ......................................................................................... 881

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