H8SX1663 datasheet(10/1158 Pages) RENESAS

10 / 1158 page

Rev.1.00 Jun. 07, 2006 Page x of lii

2.8.3

or @(d:32, ERn) .................................................................................................... 56

2.8.4

Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B),

@(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)..................... 56

2.8.5

or Post-Decrement—@ERn

+, @−ERn, @+ERn, or @ERn− ................................ 57

2.8.6

Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32....................................... 58

2.8.7

Immediate—#xx ..................................................................................................... 59

2.8.8

Program-Counter Relative—@(d:8, PC) or @(d:16, PC)....................................... 59

2.8.9

Program-Counter Relative with Index Register—@(RnL.B, PC), @(Rn.W, PC),

or @(ERn.L, PC) .................................................................................................... 59

2.8.10 Memory Indirect—@@aa:8 ................................................................................... 60

2.8.11 Extended Memory Indirect—@@vec:7 ................................................................. 61

2.8.12 Effective Address Calculation ................................................................................ 61

2.8.13 MOVA Instruction.................................................................................................. 63

2.9

Processing States.................................................................................................................. 64

Section 3 MCU Operating Modes ....................................................................... 65

3.1

Operating Mode Selection ................................................................................................... 65

3.2

Register Descriptions ...........................................................................................................66

3.2.1

Mode Control Register (MDCR) ............................................................................ 66

3.2.2

System Control Register (SYSCR) ......................................................................... 68

3.3

Operating Mode Descriptions .............................................................................................. 70

3.3.1

Mode 2.................................................................................................................... 70

3.3.2

Mode 4.................................................................................................................... 70

3.3.3

Mode 5.................................................................................................................... 70

3.3.4

Mode 6.................................................................................................................... 71

3.3.5

Mode 7.................................................................................................................... 71

3.3.6

Pin Functions .......................................................................................................... 72

3.4

Address Map ........................................................................................................................ 73

3.4.1

Address Map........................................................................................................... 73

Section 4 Exception Handling ............................................................................. 77

4.1

Exception Handling Types and Priority............................................................................... 77

4.2

Exception Sources and Exception Handling Vector Table .................................................. 78

4.3

Reset .................................................................................................................................... 80

4.3.1

Reset Exception Handling ...................................................................................... 80

4.3.2

Interrupts after Reset............................................................................................... 81

4.3.3

On-Chip Peripheral Functions after Reset Release ................................................. 81

4.4

Traces................................................................................................................................... 83

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