H8SX1663 datasheet(94/1158 Pages) RENESAS

94 / 1158 page

Section 2 CPU

Rev.1.00 Jun. 07, 2006 Page 42 of 1102

REJ09B0294-0100

Addressing Mode

Classifi-

cation

Instruction

Size

#xx

@ERn @(d,ERn)

@(d,

RnL.B/

Rn.W/

ERn.L)

−ERn/

@ERn

−/

+ERn @aa:8

@aa:16/

@aa:32

—

BFLD

Bit

manipu-

lation

BFST

Branch

BRA/BS, BRA/BC*

BSR/BS, BSR/BC*

LDC

(CCR, EXR)

B/W*

LDC

(VBR, SBR)

STC

(CCR, EXR)

B/W*

System

control

STC

(VBR, SBR)

ANDC, ORC,

XORC

SLEEP

—

NOP

—

[Legend]

d:16 or d:32

Can be specified as a source operand.

Can be specified as a destination operand.

SD:

Can be specified as either a source or destination operand or both.

S/D:

Can be specified as either a source or destination operand.

S:4:

4-bit immediate data can be specified as a source operand.

Notes: 1. Only @aa:16 is available.

2. @ERn

+ as a source operand and @−ERn as a destination operand

3. Specified by ER5 as a source address and ER6 as a destination address for data

transfer.

4. Size of data to be added with a displacement

5. Only @ERn

− is available

6. When the number of bits to be shifted is 1, 2, 4, 8, or 16

7. When the number of bits to be shifted is specified by 5-bit immediate data or a general

8. Size of data to specify a branch condition

9. Byte when immediate or register direct, otherwise, word

10. Only @ERn

+ is available

11. Only @

−ERn is available

12. Not available in this LSI.

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