H8SX1663 datasheet(33/1158 Pages) RENESAS

33 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xxxiii of x lii

Figure 6.93 Example of Idle Cycle Operation (Write after Single Address Transfer Write)...... 296

Figure 6.94 Idle Cycle Insertion Example .................................................................................. 297

Figure 6.95 Relationship between Chip Select (

CS) and Read (RD)..........................................298

Figure 6.96 Example of DRAM Full Access after External Read (CAST = 0) .......................... 299

Figure 6.97 Example of SDRAM Full Access after External Read (CAS Latency = 2) ............ 300

Figure 6.98 Example of Idle Cycles in RAS Down Mode (Write after Read)............................ 301

Figure 6.99 Bus Released State Transition Timing (SRAM Interface is Not Used)................... 306

Figure 6.100 Bus Released State Transition Timing (SRAM Interface is Used)........................ 307

Figure 6.101 Example of Timing when Write Data Buffer Function is Used ............................ 309

Figure 6.102 Example of Timing when Peripheral Module

Write Data Buffer Function is Used ..................................................................... 310

Section 7 DMA Controller (DMAC)

Figure 7.1 Block Diagram of DMAC ......................................................................................... 319

Figure 7.2 Example of Signal Timing in Dual Address Mode.................................................... 344

Figure 7.3 Operations in Dual Address Mode ............................................................................ 344

Figure 7.4 Data Flow in Single Address Mode........................................................................... 345

Figure 7.5 Example of Signal Timing in Single Address Mode ................................................. 346

Figure 7.6 Operations in Single Address Mode.......................................................................... 346

Figure 7.7 Example of Signal Timing in Normal Transfer Mode............................................... 347

Figure 7.8 Operations in Normal Transfer Mode ....................................................................... 348

Figure 7.9 Operations in Repeat Transfer Mode......................................................................... 349

Figure 7.10 Operations in Block Transfer Mode ........................................................................ 350

Figure 7.11 Operation in Single Address Mode in Block Transfer Mode

(Block Area Specified) ........................................................................................... 350

Figure 7.12 Operation in Dual Address Mode in Block Transfer Mode

(Block Area Not Specified) .................................................................................... 351

Figure 7.13 Example of Timing in Cycle Stealing Mode ........................................................... 355

Figure 7.14 Example of Timing in Burst Mode.......................................................................... 355

Figure 7.15 Example of Extended Repeat Area Operation......................................................... 357

Figure 7.16 Example of Extended Repeat Area Function in Block Transfer Mode ................... 358

Figure 7.17 Address Update Method .......................................................................................... 359

Figure 7.18 Operation of Offset Addition................................................................................... 360

Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode.......... 361

Figure 7.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode ......... 362

Figure 7.21 Procedure for Changing Register Setting For Channel being Transferred .............. 366

Figure 7.22 Example of Timing for Channel Priority................................................................. 369

Figure 7.23 Example of Bus Timing of DMA Transfer.............................................................. 370

Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing......................... 371

Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing

(Transfer Source DSAR = Odd Address and Source Address Increment).............. 372

H8SX1663 数据表(PDF) 33 Page - Renesas Technology Corp

H8SX1663 数据表(HTML) 33 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载