H8SX1663 datasheet(73/1158 Pages) RENESAS

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Section 2 CPU

Rev.1.00 Jun. 07, 2006 Page 21 of 1102

REJ09B0294-0100

Section 2 CPU

The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward

compatible with the H8/300, H8/300H, and H8S CPUs.

The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space,

and is ideal for a realtime control system.

2.1

Features

• Upward-compatible with H8/300, H8/300H, and H8S CPUs

 Can execute H8/300, H8/300H, and H8S/2000 object programs

• Sixteen 16-bit general registers

 Also usable as sixteen 8-bit registers or eight 32-bit registers

• 87 basic instructions

 8/16/32-bit arithmetic and logic instructions

 Multiply and divide instructions

 Bit field transfer instructions

 Powerful bit-manipulation instructions

 Bit condition branch instructions

 Multiply-and-accumulate instruction

• Eleven addressing modes

 Register direct [Rn]

 Register indirect [@ERn]

 Register indirect with displacement [@(d:2,ERn), @(d:16,ERn), or @(d:32,ERn)]

 Index register indirect with displacement [@(d:16,RnL.B), @(d:32,RnL.B),

@(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)]

 Register indirect with pre-/post-increment or pre-/post-decrement [@+ERn, @−ERn,

@ERn

+, or @ERn−]

 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]

 Immediate [#xx:3, #xx:4, #xx:8, #xx:16, or #xx:32]

 Program-counter relative [@(d:8,PC) or @(d:16,PC)]

 Program-counter relative with index register [@(RnL.B,PC), @(Rn.W,PC), or

@(ERn.L,PC)]

 Memory indirect [@@aa:8]

 Extended memory indirect [@@vec:7]

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