H8SX1663 datasheet(40/1158 Pages) RENESAS

40 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xl of lii

Figure 17.4 I2C Bus Timing........................................................................................................ 833

Figure 17.5 Master Transmit Mode Operation Timing 1............................................................ 835

Figure 17.6 Master Transmit Mode Operation Timing 2............................................................ 835

Figure 17.7 Master Receive Mode Operation Timing 1 ............................................................. 837

Figure 17.8 Master Receive Mode Operation Timing 2 ............................................................. 838

Figure 17.9 Slave Transmit Mode Operation Timing 1.............................................................. 839

Figure 17.10 Slave Transmit Mode Operation Timing 2............................................................ 840

Figure 17.11 Slave Receive Mode Operation Timing 1 ............................................................. 841

Figure 17.12 Slave Receive Mode Operation Timing 2 ............................................................. 842

Figure 17.13 Block Diagram of Noise Canceler......................................................................... 842

Figure 17.14 Sample Flowchart of Master Transmit Mode........................................................ 843

Figure 17.15 Sample Flowchart for Master Receive Mode ........................................................ 844

Figure 17.16 Sample Flowchart for Slave Transmit Mode......................................................... 845

Figure 17.17 Sample Flowchart for Slave Receive Mode .......................................................... 846

Figure 17.18 Timing of the Bit Synchronous Circuit ................................................................. 848

Section 18 A/D Converter

Figure 18.1 Block Diagram of A/D Converter ........................................................................... 850

Figure 18.2 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ............ 857

Figure 18.3 Example of A/D Conversion

(Scan Mode, Three Channels (AN0 to AN2) Selected).......................................... 858

Figure 18.4 A/D Conversion Timing.......................................................................................... 859

Figure 18.5 External Trigger Input Timing ................................................................................ 860

Figure 18.6 A/D Conversion Accuracy Definitions.................................................................... 862

Figure 18.7 A/D Conversion Accuracy Definitions.................................................................... 862

Figure 18.8 Example of Analog Input Circuit ............................................................................ 863

Figure 18.9 Example of Analog Input Protection Circuit........................................................... 865

Figure 18.10 Analog Input Pin Equivalent Circuit ..................................................................... 865

Section 19 D/A Converter

Figure 19.1 Block Diagram of D/A Converter ........................................................................... 867

Figure 19.2 Example of D/A Converter Operation..................................................................... 871

Section 21 Flash Memory (0.18-

µm F-ZTAT Version)

Figure 21.1 Block Diagram of Flash Memory............................................................................ 876

Figure 21.2 Mode Transition of Flash Memory.......................................................................... 877

Figure 21.3 Block Structure of User MAT ................................................................................. 879

Figure 21.4 Block Structure of User MAT ................................................................................. 880

Figure 21.5 Procedure for Creating Procedure Program............................................................. 881

Figure 21.6 System Configuration in SCI Boot Mode................................................................ 903

Figure 21.7 Automatic-Bit-Rate Adjustment Operation............................................................. 904

Figure 21.8 SCI Boot Mode State Transition Diagram .............................................................. 905

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