H8SX1663 datasheet(14/1158 Pages) RENESAS

14 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xiv of lii

6.10.10 Controlling Byte and Word Accesses ................................................................... 238

6.10.11 Burst Access Operation ........................................................................................ 240

6.10.12 Refresh Control..................................................................................................... 246

6.10.13 DRAM Interface and Single Address Transfer by DMAC ................................... 251

6.11

Synchronous DRAM Interface........................................................................................... 254

6.11.1 Setting SDRAM space .......................................................................................... 254

6.11.2 Address Multiplexing ........................................................................................... 255

6.11.3 Data Bus ............................................................................................................... 255

6.11.4 I/O Pins Used for DRAM Interface ...................................................................... 256

6.11.5 Basic Timing......................................................................................................... 257

6.11.6 CAS Latency Control............................................................................................ 259

6.11.7 Controlling Row Address Output Cycle ............................................................... 261

6.11.8 Controlling Precharge Cycle................................................................................. 263

6.11.9 Controlling Clock Suspend Insertion.................................................................... 265

6.11.10 Controlling Write-Precharge Delay ...................................................................... 266

6.11.11 Controlling Byte and Word Accesses ................................................................... 267

6.11.12 Fast-Page Access Operation ................................................................................. 269

6.11.13 Refresh Control..................................................................................................... 275

6.11.14 Setting SDRAM Mode Register ........................................................................... 281

6.11.15 SDRAM Interface and Single Address Transfer by DMAC................................. 282

6.12

Idle Cycle........................................................................................................................... 291

6.12.1 Operation .............................................................................................................. 291

6.12.2 Pin States in Idle Cycle ......................................................................................... 303

6.13

Bus Release........................................................................................................................ 304

6.13.1 Operation .............................................................................................................. 304

6.13.2 Pin States in External Bus Released State ............................................................ 305

6.13.3 Transition Timing ................................................................................................. 306

6.14

Internal Bus........................................................................................................................ 308

6.14.1 Access to Internal Address Space ......................................................................... 308

6.15

Write Data Buffer Function ............................................................................................... 309

6.15.1 Write Data Buffer Function for External Data Bus .............................................. 309

6.15.2 Write Data Buffer Function for Peripheral Modules ............................................ 310

6.16

Bus Arbitration .................................................................................................................. 311

6.16.1 Operation .............................................................................................................. 311

6.16.2 Bus Transfer Timing............................................................................................. 312

6.17

Bus Controller Operation in Reset ..................................................................................... 314

6.18

Usage Notes ....................................................................................................................... 314

Section 7 DMA Controller (DMAC)................................................................. 317

7.1

Features.............................................................................................................................. 317

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