H8SX1663 datasheet(16/1158 Pages) RENESAS

16 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xvi of lii

8.2.7

DTC enable registers A to E, G, and H (DTCERA to DTCERE, DTCERG,

and DTCERH) ...................................................................................................... 402

8.2.8

DTC Control Register (DTCCR) .......................................................................... 403

8.2.9

DTC Vector Base Register (DTCVBR)................................................................ 405

8.3

Activation Sources ............................................................................................................. 405

8.4

Location of Transfer Information and DTC Vector Table ................................................. 405

8.5

Operation ........................................................................................................................... 409

8.5.1

Bus Cycle Division ............................................................................................... 411

8.5.2

Transfer Information Read Skip Function ............................................................ 413

8.5.3

Transfer Information Writeback Skip Function.................................................... 414

8.5.4

Normal Transfer Mode ......................................................................................... 414

8.5.5

Repeat Transfer Mode .......................................................................................... 415

8.5.6

Block Transfer Mode ............................................................................................ 417

8.5.7

Chain Transfer ...................................................................................................... 418

8.5.8

Operation Timing.................................................................................................. 419

8.5.9

Number of DTC Execution Cycles ....................................................................... 421

8.5.10 DTC Bus Release Timing ..................................................................................... 422

8.5.11 DTC Priority Level Control to the CPU ............................................................... 422

8.6

DTC Activation by Interrupt.............................................................................................. 423

8.7

Examples of Use of the DTC ............................................................................................. 424

8.7.1

Normal Transfer Mode ......................................................................................... 424

8.7.2

Chain Transfer ...................................................................................................... 424

8.7.3

Chain Transfer when Counter = 0......................................................................... 425

8.8

Interrupt Sources................................................................................................................ 427

8.9

Usage Notes ....................................................................................................................... 427

8.9.1

Module Stop State Setting .................................................................................... 427

8.9.2

On-Chip RAM ...................................................................................................... 427

8.9.3

DMAC Transfer End Interrupt.............................................................................. 427

8.9.4

DTCE Bit Setting.................................................................................................. 427

8.9.5

Chain Transfer ...................................................................................................... 428

8.9.6

Transfer Information Start Address, Source Address,

and Destination Address ....................................................................................... 428

8.9.7

Transfer Information Modification ....................................................................... 428

8.9.8

Endian Format ...................................................................................................... 428

Section 9 I/O Ports............................................................................................. 429

9.1

Register Descriptions ......................................................................................................... 436

9.1.1

Data Direction Register (PnDDR) (n = 1, 2, 3, 6, A to F, H, I, and M) ................ 437

9.1.2

Data Register (PnDR) (n = 1, 2, 3, 6, A to F, H, I, and M)................................... 438

9.1.3

Port Register (PORTn) (n = 1, 2, 3, 5, 6, A to F, H, I, and M) ............................. 438

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