H8SX1663 datasheet(13/1158 Pages) RENESAS

13 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xiii of lii

6.6.6

Extension of Chip Select (

CS) Assertion Period................................................... 202

6.6.7

DACK Signal Output Timing ............................................................................... 204

6.7

Byte Control SRAM Interface ........................................................................................... 205

6.7.1

Byte Control SRAM Space Setting....................................................................... 205

6.7.2

Data Bus................................................................................................................ 205

6.7.3

I/O Pins Used for Byte Control SRAM Interface ................................................. 206

6.7.4

Basic Timing......................................................................................................... 207

6.7.5

Wait Control ......................................................................................................... 209

6.7.6

Read Strobe (

RD).................................................................................................. 211

6.7.7

Extension of Chip Select (

CS) Assertion Period................................................... 211

6.7.8

DACK Signal Output Timing ............................................................................... 211

6.8

Burst ROM Interface.......................................................................................................... 213

6.8.1

Burst ROM Space Setting ..................................................................................... 213

6.8.2

Data Bus................................................................................................................ 213

6.8.3

I/O Pins Used for Burst ROM Interface................................................................ 214

6.8.4

Basic Timing......................................................................................................... 215

6.8.5

Wait Control ......................................................................................................... 217

6.8.6

Read Strobe (

RD) Timing..................................................................................... 217

6.8.7

Extension of Chip Select (

CS) Assertion Period................................................... 217

6.9

Address/Data Multiplexed I/O Interface ............................................................................ 218

6.9.1

Address/Data Multiplexed I/O Space Setting ....................................................... 218

6.9.2

Address/Data Multiplex ........................................................................................ 218

6.9.3

Data Bus................................................................................................................ 218

6.9.4

I/O Pins Used for Address/Data Multiplexed I/O Interface .................................. 219

6.9.5

Basic Timing......................................................................................................... 220

6.9.6

Address Cycle Control.......................................................................................... 222

6.9.7

Wait Control ......................................................................................................... 223

6.9.8

Read Strobe (

RD) Timing.................................................................................... 223

6.9.9

Extension of Chip Select (

CS) Assertion Period................................................... 225

6.9.10

DACK Signal Output Timing ............................................................................... 227

6.10

DRAM Interface ................................................................................................................ 228

6.10.1 Setting DRAM Space............................................................................................ 228

6.10.2 Address Multiplexing............................................................................................ 228

6.10.3 Data Bus................................................................................................................ 229

6.10.4 I/O Pins Used for DRAM Interface ...................................................................... 229

6.10.5 Basic Timing......................................................................................................... 230

6.10.6 Controlling Column Address Output Cycle.......................................................... 231

6.10.7 Controlling Row Address Output Cycle ............................................................... 232

6.10.8 Controlling Precharge Cycle................................................................................. 234

6.10.9 Wait Control ......................................................................................................... 235

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