H8SX1663 datasheet(41/1158 Pages) RENESAS

41 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xli of x lii

Figure 21.9 System Configuration in USB Boot Mode .............................................................. 907

Figure 21.10 USB Boot Mode State Transition Diagram ........................................................... 909

Figure 21.11 Programming/Erasing Flow................................................................................... 911

Figure 21.12 RAM Map when Programming/Erasing is Executed ............................................ 912

Figure 21.13 Programming Procedure in User Program Mode .................................................. 913

Figure 21.14 Erasing Procedure in User Program Mode ............................................................ 918

Figure 21.15 Repeating Procedure of Erasing, Programming,

and RAM Emulation in User Program Mode ....................................................... 920

Figure 21.16 Transitions to Error Protection State ..................................................................... 926

Figure 21.17 RAM Emulation Flow ........................................................................................... 927

Figure 21.18 Address Map of Overlaid RAM Area (H8SX/1663) ............................................. 928

Figure 21.19 Programming Tuned Data (H8SX/1663)............................................................... 929

Figure 21.20 Boot Program States .............................................................................................. 931

Figure 21.21 Bit-Rate-Adjustment Sequence ............................................................................. 932

Figure 21.22 Communication Protocol Format .......................................................................... 933

Figure 21.23 New Bit-Rate Selection Sequence......................................................................... 944

Figure 21.24 Programming Sequence......................................................................................... 947

Figure 21.25 Erasure Sequence .................................................................................................. 947

Section 22 Clock Pulse Generator

Figure 22.1 Block Diagram of Clock Pulse Generator ............................................................... 958

Figure 22.2 Connection of Crystal Resonator (Example)........................................................... 963

Figure 22.3 Crystal Resonator Equivalent Circuit ...................................................................... 964

Figure 22.4 External Clock Input (Examples) ............................................................................ 964

Figure 22.5 External Clock Input Timing................................................................................... 965

Figure 22.6 Connection Example of 32.768-kHz Crystal Resonator.......................................... 965

Figure 22.7 Equivalent Circuit for 32.768-kHz Crystal Resonator............................................. 966

Figure 22.8 Pin Handling when Subclock is not Used ............................................................... 966

Figure 22.9 Clock Modification Timing..................................................................................... 968

Figure 22.10 Note on Board Design for Oscillation Circuit ....................................................... 968

Figure 22.11 Recommended External Circuitry for PLL Circuit................................................ 969

Section 23 Power-Down Modes

Figure 23.1 Mode Transitions..................................................................................................... 973

Figure 23.2 Software Standby Mode Application Example ....................................................... 986

Figure 23.3 Hardware Standby Mode Timing ............................................................................ 987

Figure 23.4 Timing Sequence at Power-On................................................................................ 988

Figure 23.5 When Canceling Factor Interrupt is Generated

after SLEEP Instruction Execution ......................................................................... 990

Figure 23.6 When Canceling Factor Interrupt is Generated Immediately before SLEEP

Instruction Execution (Sleep Instruction Exception Handling Not Initiated) ......... 990

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