H8SX1663 datasheet(18/1158 Pages) RENESAS

18 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xviii of lii

10.3.5 Timer Status Register (TSR)................................................................................. 530

10.3.6 Timer Counter (TCNT)......................................................................................... 534

10.3.7 Timer General Register (TGR) ............................................................................. 534

10.3.8 Timer Start Register (TSTR) ................................................................................ 535

10.3.9 Timer Synchronous Register (TSYR)................................................................... 536

10.4

Operation ........................................................................................................................... 537

10.4.1 Basic Functions..................................................................................................... 537

10.4.2 Synchronous Operation......................................................................................... 543

10.4.3 Buffer Operation................................................................................................... 545

10.4.4 Cascaded Operation .............................................................................................. 549

10.4.5 PWM Modes ......................................................................................................... 551

10.4.6 Phase Counting Mode........................................................................................... 556

10.5

Interrupt Sources................................................................................................................ 563

10.6

DTC Activation.................................................................................................................. 565

10.7

DMAC Activation.............................................................................................................. 565

10.8

A/D Converter Activation.................................................................................................. 565

10.9

Operation Timing............................................................................................................... 566

10.9.1 Input/Output Timing ............................................................................................. 566

10.9.2 Interrupt Signal Timing ........................................................................................ 570

10.10 Usage Notes ....................................................................................................................... 574

10.10.1 Module Stop State Setting .................................................................................... 574

10.10.2 Input Clock Restrictions ....................................................................................... 574

10.10.3 Caution on Cycle Setting ...................................................................................... 575

10.10.4 Conflict between TCNT Write and Clear Operations........................................... 575

10.10.5 Conflict between TCNT Write and Increment Operations ................................... 576

10.10.6 Conflict between TGR Write and Compare Match............................................... 576

10.10.7 Conflict between Buffer Register Write and Compare Match.............................. 577

10.10.8 Conflict between TGR Read and Input Capture ................................................... 578

10.10.9 Conflict between TGR Write and Input Capture .................................................. 579

10.10.10 Conflict between Buffer Register Write and Input Capture................................ 580

10.10.11 Conflict between Overflow/Underflow and Counter Clearing ........................... 581

10.10.12 Conflict between TCNT Write and Overflow/Underflow .................................. 582

10.10.13 Multiplexing of I/O Pins ..................................................................................... 582

10.10.14 Interrupts and Module Stop Mode ...................................................................... 582

Section 11 Programmable Pulse Generator (PPG) ............................................ 583

11.1

Features.............................................................................................................................. 583

11.2

Input/Output Pins ............................................................................................................... 584

11.3

Register Descriptions ......................................................................................................... 585

11.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ......................................... 585

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