H8SX1663 datasheet(24/1158 Pages) RENESAS

24 / 1158 page

Rev.1.00 Jun. 07, 2006 Page xxiv of lii

16.8.2 DMA Transfer for Endpoint 1 .............................................................................. 809

16.8.3 DMA Transfer for Endpoint 2 .............................................................................. 810

16.9

Example of USB External Circuitry .................................................................................. 811

16.10 Usage Notes ....................................................................................................................... 813

16.10.1 Receiving Setup Data............................................................................................ 813

16.10.2 Clearing the FIFO ................................................................................................. 813

16.10.3 Overreading and Overwriting the Data Registers ................................................. 813

16.10.4 Assigning Interrupt Sources to EP0 ...................................................................... 814

16.10.5 Clearing the FIFO When DMA Transfer is Enabled ............................................ 814

16.10.6 Notes on TR Interrupt ........................................................................................... 814

16.10.7 Restrictions on Peripheral Module Clock (P

φ) Operating Frequency................... 815

Section 17 I

2C Bus Interface 2 (IIC2)................................................................817

17.1

Features.............................................................................................................................. 817

17.2

Input/Output Pins ............................................................................................................... 819

17.3

Register Descriptions ......................................................................................................... 820

17.3.1 I

2C Bus Control Register A (ICCRA) ................................................................... 821

17.3.2 I

2C Bus Control Register B (ICCRB) ................................................................... 822

17.3.3 I

2C Bus Mode Register (ICMR)............................................................................ 824

17.3.4 I

2C Bus Interrupt Enable Register (ICIER)........................................................... 825

17.3.5 I

2C Bus Status Register (ICSR)............................................................................. 828

17.3.6 Slave Address Register (SAR).............................................................................. 831

17.3.7 I

2C Bus Transmit Data Register (ICDRT) ............................................................ 832

17.3.8 I

2C Bus Receive Data Register (ICDRR).............................................................. 832

17.3.9 I

2C Bus Shift Register (ICDRS)............................................................................ 832

17.4

Operation ........................................................................................................................... 833

17.4.1 I

2C Bus Format...................................................................................................... 833

17.4.2 Master Transmit Operation ................................................................................... 834

17.4.3 Master Receive Operation .................................................................................... 836

17.4.4 Slave Transmit Operation ..................................................................................... 838

17.4.5 Slave Receive Operation....................................................................................... 841

17.4.6 Noise Canceler...................................................................................................... 842

17.4.7 Example of Use..................................................................................................... 843

17.5

Interrupt Request................................................................................................................ 847

17.6

Bit Synchronous Circuit..................................................................................................... 847

17.7

Usage Notes ....................................................................................................................... 848

Section 18 A/D Converter ................................................................................. 849

18.1

Features.............................................................................................................................. 849

18.2

Input/Output Pins ............................................................................................................... 851

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