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H8SX1663 数据表(PDF) 375 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 375 Page - Renesas Technology Corp |
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375 / 1158 page ![]() Section 7 DMA Controller (DMAC) Rev.1.00 Jun. 07, 2006 Page 323 of 1102 REJ09B0294-0100 7.3.2 DMA Destination Address Register (DDAR) DDAR is a 32-bit readable/writable register that specifies the transfer destination address. DDAR updates the transfer destination address every time data is transferred. When DSAR is specified as the source address (the DIRS bit in DACR is 0) in single address mode, DDAR is ignored. Although DDAR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. 31 0 R/W 30 0 R/W 29 0 R/W 28 0 R/W 27 0 R/W 24 0 R/W 26 0 R/W 25 0 R/W Bit Bit Name Initial Value R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 16 0 R/W 18 0 R/W 17 0 R/W Bit Bit Name Initial Value R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 8 0 R/W 10 0 R/W 9 0 R/W Bit Bit Name Initial Value R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 0 0 R/W 2 0 R/W 1 0 R/W Bit Bit Name Initial Value R/W |
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