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TNETV1002IDZHK 数据表(PDF) 18 Page - Texas Instruments |
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TNETV1002IDZHK 数据表(HTML) 18 Page - Texas Instruments |
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18 / 102 page  Introduction 8 June 2001 -- Revised December 2002 SPRS180C Table 2--2. Terminal Functions (Continued) TERMINAL NAME DESCRIPTION I/O/Z† MCUEN0 O SPI enable trigger (edge/level, positive/negative) CRS0 I MII0 carrier sense COL0 I MII0 collision TXD00--TXD03 O MII0 TX data bit 0 through MII0 TX data bit 3 TXEN0 O MII0 TX enable TCLK0 I MII0 TX clock TXER0 O MII0 TX error RXER0 I MII0 RX error RCLK0 I MII0 RX clock RXDV0 I MII0 RX data valid RXD00 -- RXD03 I MII0 RX data bit 0 through MII0 RX data bit 3 EMU0--EMU1 I/O Test emulation pins 0 and 1, active-low TRST I Test reset input, active-low. A pulldown resistor is suggested to allow both normal device operation and emulation. TCK I Test Clock TDI I Test Data Input TDO O Test Data Output TMS I Test Mode Select REFCLK I Reference input clock RESET I Chip power-on reset, active-low§¶ RESET_OUT O Reset to external peripherals, active-low ADD00/ SDRAM_A00 -- ADD12/SDRAM_A12 O MCU address bus bits 0 through 12 for Flash, SRAM, and SDRAM ADD13--ADD17 O MCU address bus bits 13 through 17 for Flash and SRAM ADD18/ SDRAM_BA0 O MCU address bus bit 18 for Flash and SRAM or SDRAM BA0 signal ADD19/ SDRAM_BA1 O MCU address bus bit 19 for Flash and SRAM or SDRAM BA1 signal ADD20/ SDRAM_WE O MCU address bus bit 20 for Flash and SRAM or active-low SDRAM WE signal ADD21/ SDRAM_CAS O MCU address bus bit 21 for Flash and SRAM or active-low SDRAM CAS signal ADD22/ SDRAM_RAS O MCU address bus bit 22 for Flash and SRAM or active-low SDRAM RAS signal CS4/ BIGEND I/O MCU Chip Select 4 (active-high).§ This pin is sampled at the RESET rising edge to determine the endian mode as defined below: 0 = Little Endian 1 = Big Endian For best results, an external pullup or pulldown should be installed to ensure proper sampling. DATA00--DATA31 I/O MCU data bus bits 0 through 31 for Flash, SRAM, and SDRAM BE0/ SDRAM_DQM0 O MCU byte-enable for non-SDRAM cycles, or SDRAM byte-enable (for read) and mask (for write), active-low BE1/ SDRAM_DQM1 O MCU byte-enable for non-SDRAM cycles, or SDRAM byte-enable (for read) and mask (for write), active-low BE2/ SDRAM_DQM2 O MCU byte-enable for non-SDRAM cycles, or SDRAM byte-enable (for read) and mask (for write), active-low † I = input, O = output, Z = high-impedance ‡ The KBGPIO[15:8] pins include integrated pullup resistors. § The ARM7TDMI core can operate in either little- or big-endian mode. The 5471 configures the ARM7TDMI core’s endianness by sampling this pin at the RESET rising edge. ¶ 5471 only supports MCU boot from a 16-bit or a 32-bit-wide memory implementation on CS0. The 5471 configures the ARM7TDMI starting instruction size, and width of memory connected to CS0, by sampling this pin at the RESET rising edge. |
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