TNETV1002IDZHK datasheet(33/102 Pages) TI1

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DSP Subsystem Functional Overview

June 2001 -- Revised December 2002

SPRS180C

3.4.2 DSP Direct Memory Access (DMA) Controller

The DSP subsystem includes a six-channel DMA controller, for performing data transfers independent of the

DSP. There are several limitations that the 5471 DMA controller places on its DMA transfers. The DMA

controller has no access to the RAMs that are normally in program space, cannot access RAMs that are

implemented in the MCU subsystem, and cannot access the RAM block in DSP data space that is connected

to the API interface. The DMA controller cannot transfer between the McBSP DRR and DXR registers, nor

can it transfer between McBSP DRR or DXR registers and external resources. The DMA controller cannot

perform 32-bit accesses to external resources.

3.4.2.1

DMA Controllers View of the DSP Memory Map

Note that the DMA controller has access only to the data space DARAM at 0x0080 to 0x1FFF and the data

space SARAMs that are at 0x4000 to 0x7FFF. It does not have access to any of the SARAMs in program

space between 0x6000 and 0xFFFF, or to the API DARAM at 0x2000 to 0x3FFF. The API module has access

to the 8K x 16 DARAM block at data space 0x2000 to 0x3FFF. Note also that the DMA controller can access

external data space devices with extended addressing, while the DSP can only access page 0 of external data

space.

3.4.2.2

DSP DMA External Access

The DMA supports external accesses to extended program space, extended data space, and extended I/O

space.

•

No more than one channel may be programmed for external writes at any time

•

No more than one channel may be programmed for external reads at any time

•

Only single-word transfers are supported for external accesses.

•

The DMA does not support transfers from peripherals to external memory.

•

The DMA does not support transfers from external memory to the peripherals.

3.4.2.3

DSP DMA Transfers in Doubleword Mode (Internal Only)

Doubleword mode allows the DMA to transfer 32-bit words in any index mode. In doubleword mode, two

consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated

following each transfer. In this mode, each 32-bit word is considered to be one element.

3.4.2.4

DSP DMA Interrupts

The ability of the DMA to interrupt the DSP based on the status of the data transfer is configurable and is

determined by the IMOD and DINM bits in the DMA channel mode control register (DMMCRn). The available

modes are shown in Table 3--8.

Table 3--8. DMA Interrupts

MODE

DINM

IMOD

INTERRUPT

ABU (non-decrement)

At full buffer only

ABU (non-decrement)

At half buffer and full buffer

Multi-Frame

At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)

Multi-Frame

At end of frame and end of block (DMCTRn = 0)

ABU or Multi-Frame

No interrupt generated

ABU or Multi-Frame

No interrupt generated

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