TNETV1002IDZHK datasheet(32/102 Pages) TI1

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DSP Subsystem Functional Overview

June 2001 -- Revised December 2002

SPRS180C

3.4

DSP Peripherals

The following section describes how the 5471 DSP subsystem peripherals differ from standard peripherals

as found on the TMS320VC5409.

3.4.1 Multichannel Buffered Serial Port (McBSP)

The 5471 provides high-speed, full-duplex serial ports that are similar to those found on the 5409 device. They

allow direct interface to other 54x devices, codecs, and other devices in a system. There are two multichannel

buffered serial ports (McBSPs) within the DSP subsystem.

3.4.1.1

Deriving Sample Clock from an External Clock

To accommodate applications that require an external reference clock to be divided down to create the frame

sync clock and internal sample rate clock, the 5471 McBSP allows either the receive clock pin (BCLKR) or

the transmit clock pin (BCLKX) to be configured as the input clock to the sample rate generator. This

enhancement is enabled through two register bits: pin control register (PCR) bit 7 [enhanced sample clock

mode (SCLKME)] and sample rate generator register 2 (SRGR2) bit 13 [McBSP sample rate generator clock

mode (CLKSM)]. SCLKME is an addition to the PCR contained in the McBSPs on previous TMS320C5000™

DSP platform devices. The new bit layout of the PCR is shown in Figure 3--6. For a description of the remaining

bits, see TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302).

Reserved

XIOEN

RIOEN

FSXM

FSRM

CLKXM

CLKRM

543

SCLKME

CLKS STAT

DX STAT

DR STAT

FSXP

FSRP

CLKXP

CLKRP

LEGEND: R = Read, W = Write

Figure 3--6. Pin Control Register (PCR)

The selection of the sample rate generator (SRG) clock input source is made by the combination of the

CLKSM and SCLKME bit values as shown in Table 3--7.

Table 3--7. Sample Rate Generator Clock Source Selection

SCLKME

CLKSM

SRG CLOCK SOURCE

Reserved

DSP_CPU clock

BCLKR pin

BCLKX pin

When either of the bidirectional pins, BCLKR or BCLKX, is configured as the clock input, its output buffer is

automatically disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKR pin is configured as the

SRG input. In this case, both the transmitter and receiver circuits can be synchronized to the SRG output by

setting the PCR bits (9:8) for CLKXM = 1 and CLKRM = 1. However, the SRG output is only driven onto the

BCLKX pin since the BCLKR pin is used in input mode.

TMS320C5000 is a trademark of Texas Instruments.

TNETV1002IDZHK 数据表(PDF) 32 Page - Texas Instruments

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