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MCU Subsystem Functional Overview

June 2001 -- Revised December 2002

SPRS180C

4.3

MCU Peripherals

The following section describes the 5471 MCU subsystem peripherals.

4.3.1 MCU Ethernet Interface Module

The 5471 Ethernet interface implements an IEEE802.3/Ethernet MAC which supports 10- and 100-Mbit/s

data rates, along with buffer memory for Ethernet traffic. The 16-KB memory-mapped packet memory is used

for temporary storage of transmit (TX) and receive (RX) packets and various control information. This packet

memory is isolated from the MCU subsystem memory bus, so that Ethernet data does not affect MCU

subsystem memory access performance. Figure 4--2 is a functional block diagram of the Ethernet interface.

Local Bus

Interface

ENET0

Module

32x72--Bit

Internal

FIFO

Packet

Memory

16 KB

ARM Memory

Interface

MII0

PHY 0

Figure 4--2. Ethernet Interface Block Diagram

The Ethernet interface has two packet channels. One of these channels is associated with the Ethernet media

access controller (MAC) port (ENET0), and one virtual port connected to the logical link control layer

(sub-layer for the data link layer) of the MCU software (called MCU port). The Ethernet interface handles the

packet routing between the two packet channels.

The MAC is a full-featured, configurable 802.3 controller. The half/full duplex configuration is controlled by

setting the DUPLEX bit in the mode register. The MAC receive block implements all the required IEEE 802.3

standards for either 10Mbit/s operation or 100Mbit/s operation. The MAC receive block receives data from

the MII, handles receive path control, and identification of errors. The MAC transmit block takes the data from

the buffer memory and serializes it, and provides it to the Media Independent Interface (MII) port, following

the IEEE 802.3 standards requirements for either 10 Mbit/s operation or 100 Mbit/s operation. It implements

identification of transmit errors, and transmits the data to the MII.

When the MAC receives an Ethernet packet, the packet information is temporarily stored in a local receive

FIFO. The receive FIFO is provided to decouple system memory (packet memory) access timing from packet

timing. This prevents overrun conditions caused by MCU accesses to the packet memory. In addition to

buffering, the receive FIFO allows for network retries, runts, and flow control. Similarly, there is a transmit

FIFO for the MAC. Each of these FIFOs is 32x72, to allow buffering of a full packet plus address and control

and status information. The Ethernet interface automatically transfers data between the packet memory and

the FIFOs as necessary.

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