TNETV1002IDZHK datasheet(61/102 Pages) TI1

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Electrical Specifications

June 2001 -- Revised December 2002

SPRS180C

6.5.2 Multiply-By-N Clock Option (PLL Enabled) Timing

The frequency of the reference clock provided at the REFCLK pin can be multiplied by a factor of N to generate

the internal machine cycle. The selection of the clock mode and the value of N is described in Section 3.4.7.

NOTE: The external frequency injected must conform to specifications listed in the

Table 6--4.

Table 6--4 and Table 6--5 assume testing over recommended operating conditions and H = 0.5tc(CO)

(see Figure 6--3).

Table 6--4. Multiply-By-N Timing Requirements

MIN

MAX

UNIT

Integer PLL multiplier N (N = 1--15)†

20‡

200

tc(CI)

Cycle time, REFCLK

PLL multiplier N = x.5†

20‡

100

tc(CI)

Cycle time, REFCLK

PLL multiplier N = x.25, x.75†

20‡

tf(CI)

Fall time, REFCLK

tr(CI)

Rise time, REFCLK

tw(CIL)

Pulse duration, REFCLK low

tw(CIH)

Pulse duration, REFCLK high

† N = Multiplication factor

‡ The multiplication factor and minimum REFCLK cycle time should be chosen such that the resulting DSP_CLKOUT cycle time is within the specified

range (tc(CO)). Minimum tC(CI) for the ARM CPU is 21 ns.

Unless otherwise noted, the same switching characteristics that apply to DSP_CLKOUT also apply to

ARM_MCLK.

Table 6--5. Multiply-By-N Switching Characteristics

PARAMETER

MIN

TYP

MAX

UNIT

tc(CO)DSP

Cycle time, DSP_CLKOUT

tc(CI)/N†

tc(CO)ARM

Cycle time, ARM_MCLK

tc(CI)/N†

td(CI-CO)

Delay time, REFCLK high/low to DSP_CLKOUT high/low

tf(CO)

Fall time, DSP_CLKOUT

tr(CO)

Rise time, DSP_CLKOUT

tw(COL)

Pulse duration, DSP_CLKOUT low

H-- 2

H+ 2

tw(COH)

Pulse duration, DSP_CLKOUT high

H-- 2

H+ 2

Transitory phase, PLL lock up time

† N = Multiplication factor

tc(CO)

tc(CI)

tw(COH)

tf(CO)

tr(CO)

tf(CI)

REFCLK

DSP_CLKOUT

td(CI-CO)

tw(COL)

tr(CI)

Unstable

tw(CIH)

tw(CIL)

Figure 6--3. External Multiply-by-One Clock Timing

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